BE 5670 Exam I

Source of Silicon

Silicon dioxide (SiO2) or quartzite.

Arc Furnace Reduction

Carbon or coke is mixed with SiO2 to remove metallic impurities (SiC + SiO2 -> Si + SiO + CO).

Purity of Initial Molten Silicon

98% pure.

Electronic Grade Silicon Production

Produced via repeated fractional distillation and reduction using hydrogen.

Single Crystal vs Polycrystalline Silicon

Single crystal silicon is used for electronics, while polycrystalline silicon is used for most MEMS processes.

Advantages of Polysilicon

Overcomes processing limitations such as etch stops and anisotropic etching.

Czochralski Process

A method used to produce single-crystal silicon ingots using a starting seeding crystal.

Silicon Doping

The process of adding controllable impurities to silicon to modify its electrical properties.

N-type Silicon (Donor)

Silicon doped with an element that adds electrons (e.g., phosphorous, arsenic).

P-type Silicon (Acceptor)

Silicon doped with an element that removes electrons (e.g., boron).

Net Charge of Doped Silicon

Zero (the silicon material is not charged overall).

Polysilicon Deposition Method

Thermal decomposition or pyrolizing silane (SiH4) in a low-pressure reactor at 580-600 degrees C.

Polysilicon Deposition Reaction

SiH4 -> Si + 2H2.

Polysilicon Deposition Rate

Typically 10-20 nm/min.

Rules for Determining Miller Indices

1. Determine intercepts along axes, 2. Take reciprocals, 3. Clear fractions, 4. Reduce to lowest terms, represented as (hkl).

Miller Index Principle: Zero Value

If a Miller index is zero, the plane is parallel to that crystallographic axis.

Miller Index Principle: Size Meaning

Smaller indices mean the plane is more nearly parallel to the axis; larger indices mean it is more nearly perpendicular.

Miller Indices Example: (110)

Intercepts at a, a, infinity yield fractional intercepts 1, 1, 0.

Miller Indices Example: (111)

Intercepts at a, a, a yield fractional intercepts 1, 1, 1.

Miller Indices Example: (210)

Intercepts at a/2, a, infinity yield fractional intercepts 2, 1, 0.

Deposition

A process through which a layer of material is deposited on a surface, typically carried out by Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD).

Chemical Vapor Deposition (CVD)

A process where a substrate is heated in a chamber, precursor gases react to form a thin film, and chemical by-products are exhausted.

Low Pressure Chemical Vapor Deposition (LPCVD)

Operated at 0.1 to 10 Torr and 425-800 degrees C, allowing up to 100 wafers to be processed at a time.

Plasma Enhanced Chemical Vapor Deposition (PECVD)

Uses energy from electrons in a plasma state to deposit thin films at lower temperatures (typically 300 degrees C or room temperature).

Wet Oxidation

Uses water at high temperature to form hydroxide, yielding a higher growth rate than dry oxidation (Si + 2H2O -> SiO2 + 2H2).

Dry Oxidation

Uses a pure oxygen atmosphere at 1000-1200 degrees C to create very thin and stable oxides (Si + O2 -> SiO2).

Local Oxidation of Silicon (LOCOS)

A thermal oxidation technique where selected section(s) of silicon are selectively oxidized.

Silicon Dioxide Properties

An insulator that easily forms a stable oxide with silicon, creating a unique semiconductor-insulator combination.

Hydrofluoric Acid (HF) Etching

A highly corrosive acid that dissolves silicon dioxide (SiO2) and polycrystalline silicon, but does not attack single-crystal silicon.

Buffered Oxide Etch (BHF)

An industrial etchant composed of 6 volumes of NH4F in 1 volume of HF, used for controlled etching of oxide layers.

Piranha Etch

A 3:1 mixture of sulfuric/hydrofluoric components (HF:H2O2) used to remove organic residues and SiO2 from atmospheric oxidation.

Planar Process

Manufacturing processes such as etching and doping that happen close to the surface of the silicon.

Conformal Process

Processes such as deposition and coating that take on the shape and structure of the surface on which they are performed.

Surface Micromachining

Constructs thin mechanical components on a substrate surface by alternately depositing, patterning, and etching thin films.

Bulk Micromachining

Etches deep into a substrate to form 3D mechanical elements such as channels, chambers, and valves.

LIGA Process

Combines collimated x-ray lithography with electroplating and molding to create high aspect ratio (tall and thin) structures or deep cavities.

Thermal Evaporation

Uses a resistive filament under vacuum to heat and sublime metal, creating a vapor stream that travels in a straight line to the sample.

E-beam Evaporation

Uses a thermionic electron beam steered by a magnetic field to heat and sublime materials requiring temperatures too high for thermal evaporation.

Sputtering Mechanism

Momentum transfer where ionized inert gas atoms bombard source material to knock loose atoms; requires RF energy for insulating materials.

Key Ingredients in Wet Etchants

Consists of an oxidizer, an acid or base to dissolve the oxidized surface, and diluent media to transport reactants and products.

Silicon Anisotropic Etch Stop Planes

The (111) family of crystallographic planes acts as the stop planes for anisotropic etching due to differing hybridized orbital orientations.

KOH Etching of Silicon

A widely used hydroxide etch recipe using KOH, normal propanol, and H2O at 80°C that stops at p++ layers.

TMAH Etching Characteristics

Tetra Methyl Ammonium Hydroxide is MOS/CMOS compatible, does not significantly etch SiO2 or Al, and is bond wire safe.

Fluorine-based Plasma Etching

Dry etch method used for materials including Si, Ge, SiC, W, Nb, Mo, SiO2, and Si3N4.

Chlorine-based Plasma Etching

Dry etch method used for materials including GaAs, InP, GaN, Al, Ti, Cr, and Al2O3.

Deep Reactive Ion Etch (DRIE)

An advanced plasma etching technique used to carve deep, high-aspect-ratio structures into silicon.

Design Rules Definition

Configurations that are allowed and not allowed, determined by normal manufacturing limitations.

PolyMUMPs Design Rules Nature

Most process rules are advisory, while a few are mandatory and may not be violated.

PolyMUMPs Physical Layer: Nitride

Provides isolation between the substrate and electrical surface layers.

PolyMUMPs Physical Layer: Poly Zero

An electrical poly layer for ground plane or electrode formation below the first mechanical layer.

PolyMUMPs Physical Layer: First Oxide

First sacrificial oxide layer providing a gap between poly 1 and the substrate/nitride.

PolyMUMPs Physical Layer: Poly 1

The first mechanical layer in PolyMUMPs.

PolyMUMPs Physical Layer: Second Oxide

Second sacrificial oxide layer providing a gap between second and first polysilicon.

PolyMUMPs Physical Layer: Poly 2

The second mechanical layer in PolyMUMPs.

PolyMUMPs Physical Layer: Metal

Provides electrical connection to the package.

PolyMUMPs Lithography Level: POLY ZERO

Defines the polysilicon zero features (represented in capital letters).

PolyMUMPs Lithography Level: ANCHOR 1

Opens points-of-contact between first polysilicon and the substrate (nitride or poly 0).

PolyMUMPs Lithography Level: DIMPLE

Generates bumps in the under-surface of poly 1 to minimize stiction.

PolyMUMPs Lithography Level: POLY 1

Defines first polysilicon features.

PolyMUMPs Lithography Level: POLY1_POLY2_VIA

Opens points-of-contact between first and second polysilicon.

PolyMUMPs Lithography Level: ANCHOR 2

Opens points-of-contact between second polysilicon and substrate/nitride.

PolyMUMPs Lithography Level: POLY 2

Defines second polysilicon features.

PolyMUMPs Lithography Level: METAL

Defines the location of metal features.

Layout Terminology: Layer vs LEVEL

A physical layer uses mixed-case letters, whereas a lithographic level uses CAPITAL letters.

Layout Terminology: Dimples

Small, shallow features in the underside of the lower polysilicon layer to minimize contact area with the substrate.

Layout Terminology: PSG (Phospho-silicate-glass)

A phosphorous-containing silicon dioxide layer generated by CVD and used for its fast etching properties.

Layout Terminology: Sacrificial Oxide

A layer of fast-etching silicon dioxide used to define separation between mechanical layers and the substrate.

Layout Terminology: Stringer

A ribbon of material left behind after an RIE etch step, generally created at a topographic edge.

Layout Terminology: Lift-off

A method of depositing metal using a polymer template where subsequent solvent immersion removes the polymer and overlaying metal.

Layout Terminology: Release

The last step of the process where sacrificial layers are removed by submersion into HF.

Layout Terminology: Stiction

The sticking effect between polysilicon and the substrate which occurs during the removal of sacrificial oxide.

PolyMUMPs Process: Initial Doping

A heavily doped N+ layer (POCl3 diffusion) is diffused into the starting wafer to minimize charge feed-through.

PolyMUMPs Process: Poly 1 Deposition

Deposited by LPCVD, followed by a thin PSG layer and high-temperature anneal to reduce residual stress and dope poly 1.

PolyMUMPs Post Process: HF Release

A 2-minute soak in concentrated 49% HF at room temperature removes all sacrificial oxide layers and releases moveable mechanical parts.

PolyMUMPs Post Process: Supercritical CO2 Drying

Critical point drying that circumvents surface tension effects by avoiding the liquid/vapor interface.

Photolithography Types

Contact and projection lithography used for patterning.