Computer Arch. Ch. 3

Contemporary computer designs are based on concepts

developed by

John von Neumann at the Institute for Advanced Studies, Princeton

the von Neumann architecture is based on three key concepts:

• Data and instructions are stored in a single read-write memory

• The contents of this memory are addressable by location, without regard to the type of data contained there

• Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next

Hardwired program

The result of the process of connecting the various components in the desired configuration

What is Software

• A sequence of codes or instructions

• Part of the hardware interprets each instruction and generates control signals

• Provide a new sequence of codes for each new program instead of rewiring the hardware

Memory address register (MAR)

Specifies the address in memory for the next read or write

Memory buffer register (MBR)

Contains the data to be written into memory or receives the data read from memory

I/O address register (I/OAR)

Specifies a particular I/O device

I/O buffer register (I/OBR)

Used for the exchange of data between an I/O module and the CPU

Fetch Cycle

The fetch cycle gets the next instruction from memory by using the PC to find its address and placing the instruction into the IR. The PC is then incremented so it points to the next instruction.

Interrupt

a signal emitted by hardware or software when a process or an event needs immediate attention. It alerts the processor to a high-priority process requiring interruption of the current working process

Software Interrupts

• . Traps and exceptions are other names

• an interrupt generated within a processor by executing an instruction. E.g., system calls.

Hardware Interrupts:

• all the devices are connected to the Interrupt Request Line. A single request line is used for all the n devices.

• To request an interrupt, a device closes its associated switch.

• When a device requests an interrupt, the value of INTR is the logical OR of the requests from individual devices.

Instruction Cycle with Interrupts

1. Processor checks for interrupt

• Indicated by an interrupt signal

• If no interrupt, fetch next instruction

2. If interrupt pending:

• Process interrupt

Interrupt Processing in Detail

1. Suspend execution of current program

2. Save context (the address of next instruction and any other data)

3. Set PC to starting addr. of interrupt handler routine

4. Process interrupt (i.e., execute int. handler routine)

5. Restore context and continue interrupted program at the point of interruption

Non-Maskable Interrupt

• A special type of interrupt that can not be ignored by standard interrupt masking techniques

• Often used when response time is critical, and when an interrupt should never be disabled in the normal operation of the system

Interrupt Handler Routine

subroutine in an Operating System or device driver whose execution is

triggered by the reception of an interrup

Interrupt Vector

The memory address of an interrupt handler, or an index into an array

Interrupt number 00h to 0Fh are assigned for

hardware interrupts

Interrupt number 10h to 0FFh are assigned for

software interrupts

When multiple interrupts occur

• Low priority interrupts can be interrupted by higher priority interrupts

• Processor will ignore further interrupts whilst processing one interrupt

The interconnection structure must support the following types of transfers:

1. Memory to processor

2. Processor to memory

3. I/O to processor

4. Processor to I/O

5. I/O to or from memory

Memory to processor

Processor reads an instruction or a unit of data from memory

Processor to memory

Processor writes a unit of data to memory

I/O to processor

Processor reads data from an I/O device via an I/O module

Processor to I/O

Processor sends data to the I/O device

I/O to or from memory

An I/O module is allowed to exchange data directly with memory without going through the processor using direct memory access

Bus:

A communication pathway connecting two or more devices

System bus

A bus that connects major computer components (processor, memory, I/O)

Data Bus

 Data lines that provide a path for moving data among system modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a time

 The width of the data bus is a key factor in determining overall system performance

Address Bus

 Used to designate the source or destination of the data on the data bus

 Width determines the maximum possible memory capacity of the system

 Also used to address I/O ports

Control Bus

 Used to control the access and the use of the data and address lines

 Because the data and address lines are shared by all components there must be a means of controlling their use

 Control signals transmit both command and timing information among system modules

 Timing signals indicate the validity of data and address information

 Command signals specify operations to be performed

Point-to-point interconnection

two components are directly connected to each other by a dedicated connection.

Quick Path Interconnect

 Multiple direct connections

 Direct pairwise connections to other components eliminating the need for arbitration found in shared transmission systems

 Layered protocol architecture

 These processor level interconnects use a layered protocol architecture rather than the simple use of control signals found in shared bus arrangements

 Packetized data transfer

 Data are sent as a sequence of packets each of which includes control headers and error control codes

QPI Link Layer

Performs two key functions: flow control and error control

Flow control function for QPI Link Layer

Needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data

Error control function for QPI Link Layer

Detects and recovers from bit errors, and so isolates higher layers from experiencing bit errors

QPI Routing Layer

 Used to determine the course that a packet will traverse across the available system interconnects

 Defined by firmware and describe the possible paths that a packet can follow

QPI Protocol Layer

 Packet is defined as the unit of transfer

 One key function performed at this level is a cache coherency protocol which deals with making sure that main memory values held in multiple caches are consistent

 A typical data packet payload is a block of data being sent to or from a cache

Peripheral Component Interconnect (PCI)

 A popular high bandwidth, processor independent bus that can function as a mezzanine or peripheral bus

 Delivers better system performance for high speed I/O subsystems

PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based schemes such as PCI

 Key requirement is high capacity to support the needs of higher data rate I/O devices, such as Gigabit Ethernet

 Another requirement deals with the need to support time dependent data streams

PCIe Transaction Layer (TL)

 Receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer

 Most transactions use a split transaction technique

 A request packet is sent out by a source PCIe device which then waits for a response called a completion packet

 TL messages and some write transactions are posted transactions (meaning that no response is expected)

 TL packet format supports 32-bit memory addressing and extended 64-bit memory addressing

The TL supports four address spaces:

 Memory

 I/O

 Configuration

 Message