Computer Engineering & ARM Cortex-M0 Architecture

Vocabulary flashcards covering core CPU components, register functions, memory organization, assembly language concepts, and computer architecture fundamentals based on the lecture materials.

Core Registers (Cortex-M0)

Internal processor storage consisting of $13 \times \text{32-bit}$ registers for temporary storage (r0–r12), $1 \times \text{32-bit}$ Stack Pointer (sp / r13), $1 \times \text{32-bit}$ Link Register (lr / r14), and $1 \times \text{32-bit}$ Program Counter (pc / r15).

ALU (Arithmetic Logic Unit)

The data processing unit inside the CPU responsible for performing arithmetic and logic operations.

Flags (Processor Status Register)

Status bits inside the processor that indicate the current operational state and outcome of recent CPU operations.

Control Unit with Instruction Register

The CPU component that controls the execution of instructions based on the machine code currently held in the Instruction Register (IR).

Bus Interface

The interface between the CPU and the external System Bus, acting as a bridge between internal and external communication buses.

Program Counter (pc)

Register r15, which points to the memory address from which the next instruction will be read.

Stack Pointer (sp)

Register r13, which points to the memory address where elements are currently read from or written to the stack.

Link Register (lr)

Register r14, used to hold and keep track of return addresses to jump back to when returning from subroutines or functions.

Instruction Fetch

The phase of the processor cycle in which an instruction is retrieved from code memory.

Instruction Execute

The phase of the processor cycle where the CPU performs the actions specified by the decoded instruction.

Word (Cortex-M0)

A $\text{32-bit}$ memory unit in the ARM Cortex-M0 architecture.

Half-word (Cortex-M0)

A $\text{16-bit}$ memory unit in the ARM Cortex-M0 architecture.

Little Endian

A multi-byte data representation where the least significant byte (LSByte) is stored at the lowest memory address.

Big Endian

A multi-byte data representation where the most significant byte (MSByte) is stored at the lowest memory address.

Word Alignment

The requirement that the memory address of a multi-byte element must be an integer multiple of its word size ($4$ bytes for the Cortex-M0).

Memory Map

A graphical layout showing the addresses and sizes of all elements communicating with the CPU, including memories, inputs, and outputs.

CODE Memory Section

A read-only section located in RAM or ROM that stores machine instructions and constants.

DATA Memory Section

A read-write memory section located in RAM that contains global variables, static variables, and the C heap.

STACK Memory Section

A read-write memory section located in RAM used for procedure calls, parameter passing, and storing local variables.

Load/Store Architecture

An architecture where data processing operations occur strictly between internal registers, and memory access is performed exclusively via explicit load and store instructions.

mov vs. movs Instructions

mov transfers data between registers without modifying processor status flags (supports high and low registers), while movs modifies processor flags and is restricted to low registers.

Pseudo-Instruction

An assembly directive or instruction (such as <ldr Rn, =literal>) that does not directly map to a single machine opcode, but is expanded by the assembler into real machine instructions and literal pool allocations.

Von Neumann Architecture

A computer architecture where both program instructions and program data share and are stored within the same unified memory space.

Preprocessor

The translation tool that processes directives such as #define and #include by textual substitution, generating modified C source code.

Compiler

The tool that translates high-level C source code into processor-specific, symbolic assembly language code.

Assembler

The tool that converts symbolic assembly language instructions into binary machine instructions, creating an object file.

Linker

The software tool that merges multiple object files into a single executable binary, performing address relocation and resolving inter-file references.

Main Memory (Arbeitsspeicher)

Central system memory connected directly to the CPU via the System Bus, offering byte-level access, and categorized as volatile (SRAM, DRAM) or non-volatile (ROM, Flash).

Secondary Storage

Peripheral, non-volatile storage connected via I/O ports that is accessed in data blocks, typically slower and cheaper than main memory (e.g., hard disks, SSDs, optical media).

System Bus

The electrical interconnect between functional units (CPU, memory, and I/O) consisting of data lines, address lines, and control signals.

Relative Branch

A branching mechanism where the destination target address is calculated relative to the current value of the Program Counter (PC).

Direct vs. Indirect Branch

A direct branch contains the target address or offset as part of the instruction itself, whereas an indirect branch retrieves the target address from an internal register.