cspp topic 5

how long has clock speed been flat for?

20 years

what is the best RAM model right now?

DDR5-8800 CL36 RAM, has a first word latency of about 8ns

why is it hard to build microprocessors with high(er) clock speeds?

power consumption, speed of light /propagation issues, capacitance, it can make design of the overall package harder

with a 3GHz clock, how fast does electricity travel in one clock cycle?

less than 9cm

why is power consumption an issue when attempting to increase clock speed?

power consumption scales bad with frequency, bringing cooling problems

why would adding more cache to the processor have little benefit?

cache hit rate is asymptotic, so past a certain point it does not buy much // cache hit rates are probably as good as they are going to get

what is a stipulation with SRAM?

SRAM is quite power hungry, and we have to locate it close in to the CPU core in order to get full performance

what ae the drawbacks of making the processor ‘more complicated’?

track record is not good, increases chances of flaws in processors

what is pipelining?

improves CPU performance by overlapping the execution of multiple instructions, running a single thread (of instructions) faster by overlapping execution on available units

what is simultaneous multithreading?

run n threads on n cores, using the elements that are available in a more flexible way

what is a requirement for SMT (simultaneous multithreading)?

requires you actually have a threaded workload, which may not be the case

how is the CPU arranged today for maximum efficiency?

• each processor core is deeply pipelined

• each processor core may run more than one thread

• there will be more than one core in each package

• the OS will see multiple processors equal to threads times cores time packages

• all processors beyond the simplest are pipelined

what is macro architecture?

the high-level structure of architecture

what is mirco architecture?

the hardware-level design that implements a specific instruction set

what is the issue with pipelining?

typical programs contains loops, conditionals, function calls that may or may not happen etc, there is a lot of housekeeping in a real computer system

why do conditional branches kill pipelining?

whenever we branch in a way which depends on prior execution or events, we impact our ability to predict the next and subsequent instructions. // if branching conditionally, we will need to pause fractionally because until the condition is executed, we don’t know what to fetch next

how does a delayed branch work for BEQ?

• test whether two registers are equal by subtracting them

• branch on zero

• always do this instruction

what are RISC processors?

reduced instruction set computers (relegates interesting stuff to the compiler)

what are the downfalls of deferred branching?

• throws a lot of load onto the compiler

• simply adding one extra instruction still leaves any pipelining of more than one slot nearly empty (stalled) when the branch happens

what is branch prediction?

a way of predicting which way a branch will go, not perfectly but a ‘most of the time’ case

how does branch prediction become programmer’s responsibility?

programmer need to implement constructs such as

• if (likely(condition)) { … something that normally happens … }

• if (unlikely(condition)) { … something that rarely happens … }

how is branch prediction done in practice?

done by both compiler and processor, so having the programmer do it (often badly) is not recommended

what is the benefit of branch prediction?

allows the compiler to start fetching and processing instructions along the likely route rather than the default route

what are constraints of speculative execution?

• need to make sure that executing instructions speculatively which it later turns out shouldn't’ve been executed doesn’t affect later execution

• assumes that the speculative execution does not consume resources that might otherwise be used more productively

what are types of speculative execution?

eager execution, branch prediction, machine learning, feeding ack past runs, caching branches

what is speculative execution?

optimisation technique, involves executing tasks or instructions before knowing if they are actually needed to reduce latency and increase throughout

what is eager execution?

always executing both sides of a branch (and perhaps even all four sides of two successive branches)

how does branch prediction work?

use some metric to predict which way the branch will go, but execute both sides when unsure

what is cache?

a copy of memory but much faster

how do you store and access data from cache (generally)?

• take the address mod the size of the cache, and store the memory contents and tag (rest of the address)

• when accessing, take address mod size of cache, check whether tag matches

what is set-associative cache?

a cache mapping technique that blends the advantages of direct mapping and fully associative mapping to balance speed, flexibility and hardware cost

how is set associative cache organised?

cache is divided into sets where each set contains a fixed number of cache lines, a memory block maps to exactly one set but can be placed in any line within that set

how does set-associative cache work?

• take the address mod the number of units, store the tag and value in any available row

• look up by taking the address mod whatever and searching for any matching tag

what is the advantage and disadvantage of set associative cache?

marginally improves cache hit rate at the expense of a more complex look up

how can we tell if our data was cached?

reading the system clock before and after fetching contents of a memory location, if > 1 came from RAM, else from cache

how do some OS map OS data?

mapping it in the address space of processes, but making it only available when is supervised mode

what is a benefit of only making OS data available when in supervisor mode?

gives a useful place to put preprocess information

• eg. encryption keys (OS performs encryption but manages the keys)

how can cache be used to fetch forbidden data?

• load effective address

• load the address of the array

• add index

• fetch the result

what is SMP?

symmetric multiprocessing

what does uniprocessing mean?

where the processor is doing everything with an OS

what is asymmetric multiprocessing?

when another processor is added to do something else, with a more specific software stack

what are examples for functions a processor can take for asymmetric processing?

network acceleration, graphics acceleration, vector processing, database processing

what is symmetric processing?

the system contains multiple instances of the same processor

what is ivan sutherland’s cycle of reincarnation?

uniprocessing, asymmetric multiprocessing, symmetric multiprocessing, uniprocessing

what are the advantages and disadvantages of having more than one processor?

advantages:

• we can schedule processes onto the processors, so if there is enough application work, we can keep them busy

disadvantages:

• cache synchronisation between processors can be very difficult

• splitting I/O and other system activity between processors is difficult

for multiprocessing efficiency what is preferred in processors?

2x of power in one processor over 2 processors of power x