CSE 464 Exam 2 Symbols & Formulas Study Guide

Comprehensive vocabulary flashcards covering the 24 core symbols, timing definitions, adders and PG logic equations, and interconnect models for CSE 464 Exam 2 (Weeks 6–10).

Logical Effort ($g$)

Ratio of input capacitance of a gate to an inverter delivering equal output drive current, measuring relative current delivery capability. Derivation / Formula: $g = \frac{C_{\text{in}}}{C_{\text{in,inv}}}$ (NOR2: $5/3$, NAND2: $4/3$, INV: $1$).

Parasitic Delay ($p$)

Intrinsic delay of a logic gate driving zero external load, caused by internal self-capacitance at diffusion nodes. Derivation / Formula: $p = \frac{C_{\text{diff}}}{C_{\text{gate}}}$ (INV: $1$, NAND2: $2$, NOR2: $2$).

Stage Effort ($f$)

Total workload delay assigned to a single stage, combining its logical effort and electrical load ratio. Derivation / Formula: $f = g \times h$ (where $h = \frac{C_{\text{out}}}{C_{\text{in}}}$).

Path Electrical Effort ($H$)

Overall capacitive gain driven across a multi-stage logic network. Derivation / Formula: $H = \frac{C_{\text{out-path}}}{C_{\text{in-path}}}$.

Branching Effort ($B$)

Multiplier accounting for signal current splitting into off-path load capacitance at logic nodes. Derivation / Formula: $B = \prod b_i$, where $b_i = \frac{C_{\text{on-path}} + C_{\text{off-path}}}{C_{\text{on-path}}}$.

Total Path Effort ($F$)

Total logical and electrical burden across an entire $N$-stage path. Derivation / Formula: $F = G \times B \times H$ (where $G = \prod g_i$).

Best Stage Effort ($f■$ / $\rho$)

Optimal effort per stage that minimizes total path propagation delay across $N$ stages. Derivation / Formula: $f■ = F^{1/N}$ (Optimal target: $f■ \approx 3.59$ with $p_{\text{inv}} = 1$).

Total Path Delay ($D$)

Minimum possible propagation delay across an $N$-stage logic path in units of tau ($\tau = 3RC$). Derivation / Formula: $D = N \times f■ + \sum p_i$ (in units of $\tau$).

Rising Logical Effort ($g_u$)

Logical effort for $0 \rightarrow 1$ output transition, favored in HI-skew gates by downsizing non-critical nMOS. Derivation / Formula: $g_u = \frac{C_{\text{in,HI}}}{C_{\text{in,inv}}}$ (HI-NAND2: $1$, HI-NOR2: $3/2$).

Falling Logical Effort ($g_d$)

Logical effort for $1 \rightarrow 0$ output transition, favored in LO-skew gates by downsizing non-critical pMOS. Derivation / Formula: $g_d = \frac{C_{\text{in,LO}}}{C_{\text{in,inv}}}$ (LO-NOR2: $4/3$, LO-NAND2: $1$).

Clock-to-Q Delay ($t_{\text{pcq}}$)

Propagation delay from the active clock edge until the output $Q$ stabilizes at a valid logic state. Max Delay Limit: $T_c \ge t_{\text{pd}} + t_{\text{pcq}} + t_{\text{setup}} + t_{\text{skew}}$.

Clock-to-Q Contamination Delay ($t_{\text{ccq}}$)

Minimum time before output $Q$ begins to change after an active clock edge. Min Delay Check: $t_{\text{cd}} \ge t_{\text{hold}} - t_{\text{ccq}} + t_{\text{skew}}$.

Setup Time ($t_{\text{setup}}$)

Minimum time data input $D$ must remain stable BEFORE the active clock edge to ensure capture. Max Logic Delay: $t_{\text{pd}} \le T_c - (t_{\text{pcq}} + t_{\text{setup}} + t_{\text{skew}})$.

Hold Time ($t_{\text{hold}}$)

Minimum time data input $D$ must remain stable AFTER the active clock edge, unaffected by clock period. Min Logic Delay: $t_{\text{cd}} \ge t_{\text{hold}} - t_{\text{ccq}} + t_{\text{skew}}$.

Clock Skew ($t_{\text{skew}}$)

Spatial variation in arrival times of temporally equivalent clock edges across different flip-flops. Positive skew hurts hold time; negative skew hurts setup time.

Time Borrowing ($t_{\text{borrow}}$)

Time combinational logic in phase 1 borrows across a transparent latch boundary into phase 2. Derivation / Formula: $t_{\text{borrow}} \le \frac{T_c}{2} - (t_{\text{setup}} + t_{\text{nonoverlap}} + t_{\text{skew}})$.

Bitwise Generate ($G_i$)

Signal indicating bit $i$ unconditionally produces a carry-out regardless of carry-in. Derivation / Formula: $G_i = A_i \times B_i$.

Bitwise Propagate ($P_i$)

Signal indicating bit $i$ propagates an incoming carry-in to its carry-out. Derivation / Formula: $P_i = A_i \oplus B_i$ | Sum: $S_i = P_i \oplus C_{\text{in}}$.

Bitwise Kill ($K_i$)

Signal indicating bit $i$ absorbs and kills any carry-in (forces carry-out to $0$). Derivation / Formula: $K_i = \sim A_i \times \sim B_i = \sim (A_i + B_i)$.

Group Generate ($G_{i:j}$)

Cumulative generate signal across a block spanning bit $i$ down to bit $j$. Derivation / Formula: $G_{i:j} = G_{i:k} + P_{i:k} \times G_{k-1:j}$ | $P_{i:j} = P_{i:k} \times P_{k-1:j}$.

3-D Tree Taxonomy ($(l, f, t)$)

Classification plane for parallel prefix adders balancing logic levels ($l$), fanout ($f$), and wiring tracks ($t$). Derivation / Formula: $l + f + t = L - 1$ (where $L = \log_2(N)$).

Signed Overflow Flag ($V$)

Arithmetic overflow indicator for signed 2's complement addition. Derivation / Formula: $V = A_{n-1} \times B_{n-1} \times \sim S_{n-1} + \sim A_{n-1} \times \sim B_{n-1} \times S_{n-1} = C_n \oplus C_{n-1}$.

Sheet Resistance ($R_■$)

Resistance of a square trace of thin film conductor material, independent of square size. Derivation / Formula: $R_{\text{wire}} = R_■ \times \left(\frac{L}{W}\right)$ [units: $\Omega/■$].

Optimal Repeater Count ($N_{\text{opt}}$)

Optimal number of inverters/repeaters to insert along a wire to turn quadratic delay into linear delay. Derivation / Formula: $N_{\text{opt}} = l \times \sqrt{\frac{R_w \times C_w}{2 \times R \times C'}}$.