AVR Architecture and Assembly Language Programming

Flashcard set covering AVR microcontroller architecture, assembly instructions, memory spaces (GPRs, SFRs, SRAM, EEPROM, Flash), SREG status flags, GPIO registers, and RISC features.

General Purpose Registers (GPRs)

A small, ultra-fast memory located directly inside the CPU used to temporarily store data, addresses, and intermediate results for arithmetic and logic operations. In AVR, there are $32$ registers ($R0$ to $R31$), all of which are $8\text{-bit}$ and function like an accumulator.

LDI Instruction

An instruction that copies an $8\text{-bit}$ immediate value ($0$ to $255$ in decimal, or $\text{0x00}$ to $\text{0xFF}$ in hex) into one of the upper general purpose registers ($R16$ to $R31$). It cannot be used to load values into registers $R0$ to $R15$.

ADD Instruction

An arithmetic instruction with the format ADD Rd, Rr that instructs the CPU to add the contents of register $Rr$ to register $Rd$ and store the resulting sum in register $Rd$.

AVR Data Memory

The address space used to store data, consisting of three main parts: General Purpose Registers (GPRs), I/O memory (Special Function Registers or SFRs), and internal data SRAM.

Standard I/O Memory (SFRs)

A fixed $64\text{-byte}$ section of data memory (data addresses $\text{\$0020}$ to $\text{\$005F}$) dedicated to specific control functions of the microcontroller and its peripherals, such as timers, serial communication, I/O ports, and the status register.

Extended I/O Memory

An extra memory segment present in AVR microcontrollers with more than $32$ I/O pins (such as ATmega64, ATmega128, and ATmega256) that holds the registers used to control additional ports and peripheral functions.

Internal Data SRAM (Scratchpad)

An $8\text{-bit}$-wide volatile data memory area directly accessible by its address, widely used by programmers and C compilers for storing frequently changing data and runtime parameters.

EEPROM (in AVR)

An on-chip non-volatile memory used to store data that must not be lost when power is turned off (such as system options and settings) and that is rarely modified.

Status Register (SREG)

An $8\text{-bit}$ register containing conditional flags ($C, Z, N, V, S, H$) and control bits ($T, I$) that reflect the CPU state and the outcome of the most recently executed arithmetic or logic operation.

Carry Flag (C)

A conditional flag in SREG that is set whenever there is a carry out from the $D7$ bit during an $8\text{-bit}$ addition or subtraction; primarily used to detect errors in unsigned arithmetic.

Zero Flag (Z)

A conditional flag in SREG that reflects whether the result of an arithmetic or logic operation equals zero ($Z = 1$) or is non-zero ($Z = 0$).

Negative Flag (N)

A status flag in SREG that reflects the value of the most significant bit ($D7$) of the operation's result; set to $1$ if the signed result is negative and cleared to $0$ if positive.

Overflow Flag (V)

A status flag in SREG set whenever the result of a signed arithmetic operation is too large, causing the high-order bit to overflow into the sign bit; used to detect signed arithmetic errors.

Sign Bit (S)

A flag in SREG calculated as the Exclusive-OR (XOR) of the Negative flag ($N$) and the Overflow flag ($V$): $S = N \oplus V$.

Half Carry Flag (H)

A flag in SREG set if there is a carry from bit $D3$ to bit $D4$ during an ADD or SUB instruction; used by instructions that perform Binary Coded Decimal (BCD) arithmetic.

Global Interrupt Enable (I)

Bit $D7$ of SREG that acts as the master enable/disable switch for all interrupts ($1 = \text{Enabled}$, $0 = \text{Disabled}$); automatically cleared when an interrupt occurs and restored when the routine finishes.

Bit Copy Storage (T)

A bit in SREG utilized by the BLD (Bit Load) and BST (Bit Store) instructions to transfer a single bit back and forth between a general-purpose register and the status register.

DDRx (Data Direction Register)

An $8\text{-bit}$ read/write register used to configure individual port pins as inputs or outputs. Writing a $1$ configures a pin as an output, while writing a $0$ configures it as an input (initial default value is $0$).

PORTx (Data Register)

An $8\text{-bit}$ read/write register used to set the output logic levels of port pins. Writing a $1$ outputs a logic HIGH ($5\,\text{V}$), whereas writing a $0$ outputs a logic LOW ($0\,\text{V}$).

PINx (Input Pins Address Register)

An $8\text{-bit}$ read-only register used to read the physical logic states present on the external pins of port $x$.

Program Counter (PC)

The CPU register that points to the memory address of the next instruction to be fetched and executed from Flash ROM; automatically incremented as instructions are retrieved.

Interrupt Vector Table (IVT)

A table positioned at the beginning of Flash memory (starting at address $\text{0x0000}$) containing the entry addresses for all interrupt routines and the reset vector.

Application Program Section

The primary section of Flash memory situated directly after the Interrupt Vector Table, containing the main program execution code, subroutines, library functions, and constants.

Bootloader Section

An independently configurable section located at the highest addresses of AVR Flash memory (typically $128$, $256$, $512$, or $1024$ words) used to re-program the Application Program Section without an external hardware programmer.

Load/Store Architecture

A characteristic of RISC design where arithmetic and logic operations can only be executed between registers inside the CPU; operands from memory must first be loaded into registers before processing and stored back afterward.

Harvard Architecture

A computer architecture using physically separate memory spaces and buses for program code and data, enabling the CPU to access code and data simultaneously.