ENEL 453 Practice Questions Part 1

What does FPGA stand for?

Field Programmable Gate Array

Which company acquired Xilinx in 2022?

AMD

What is the primary building block of an FPGA?

Logic Element (LE)

What is the purpose of a Phase Locked Loop (PLL) in an FPGA?

To modify the external clock frequency

Which type of memory in an FPGA is non-volatile and can be used to store calibration values?

UFM (User Flash Memory)

What is a primary advantage of FPGAs over ASICs?

Reprogrammability

Which FPGA architecture is describes as having slices containing six-input LUTs and multiple flip-flops?

Xilinx Artix-7

Which of the following is NOT a typical peripheral found in microcontroller?

CLB

Which memory holds the bitstream that programs the FPGA at power-up?

CFM (Configuration Flash Memory)

What type of logic do Look-Up Tables (LUTs) in FPGAs implement?

Combinational logic

What is the primary advantage of using FPGAs over ASICs in prototyping?

Reduced development time

Which FPGA resource holds the LUTs and flip-flops a design’s logic is mapped onto?

Configurable Logic Blocks (CLBs)

What is the purpose of the programmable interconnect in an FPGA?

To establish connections between different logic elements within the FPGA

What is the role of Input/Output Blocks (IOBs) in an FPGA?

To interface the FPGA with the external world

Which of the following FPGA design flows involves describing the desired hardware functionality using a HDL?

RTL design flow

What is the purpose of the synthesis stage in the FPGA design flow?

To translate the HDL description into a gate-level netlist

Which of the following steps in the FPGA design flow involves mapping the gate-level netlist to the specific resources available in the target FPGA device?

Implementation

What is the final output of the FPGA design flow that is used to configure the FPGA device?

Bitstream

What does LUT stand for int he context of FPGAs?

Lookup Table

Which of the following is NOT a typical application of FPGAs?

General-purpose microprocessors

What is Dr. Mike Smith’s “first rule of assembly language programming”?

Avoid using assembly language whenever possible

What is Dr. Denis Onen’s “first rule of designing with FPGAs”?

Avoid an FPGA when a microcontroller with do

What does Amdahl’s Law primarily address in the context of parallel computing?

The theoretical limit of speedup achievable by parallelizing a portion of a computation

According to Amdahl’s Law, what is the speedup limit if 75% of a task is parallelizable and you have an infinite number of processors?

4x (hint: use the equation in notes)

If a task takes 100 seconds to complete, and 60% of it can be parallelized, what is the best possible speedup with an infinite number of processors according to Amdahl’s Law?

2.5x

Which statement best describes what Amdahl’s Law implies about adding processors?

Beyond a certain point, adding more processors yields diminishing returns

What does the term 1 - P represent in Amdahls’s Law?

The proportion of the task that is inherently sequential

Which of the following best describes the outcome as the number of processors N approaches infinity according to Amdahl’s Law?

The sequential portion of the task dominates the total time, limiting the speedup

According to Amdahl’s Law, what happens to the serial portion of a task as processors are added?

It has no effect on the execution time

In Amdahl’s Law as N becomes very large, which factor remains the primary constant of speedup?

The sequential portion of the task

What is the “continuum of configurable computing”?

A range of hardware design methodologies from fixed-function hardware to fully programmable systems

Which factor increases as you move from CPUs toward ASICs on the continuum of configurable computing?

Performance and power efficiency

Which of the following is a characteristic of systems located towards the ASIC end of the continuum of configurable computing?

High performance and low power consumption

What is a primary advantage of FPGAs within the continuum of configurable computing?

They combine high performance with reprogrammability

Which type of hardware is at the most flexible end of the continuum of configurable computing?

General-purpose CPUs

What is a key disadvantage of using ASICs compared to FPGAs in the continuum of configurable computing?

Inability to reprogram the hardware after manufacturing

On the continuum of configurable computing, what type of task is best suited for an FPGA?

A task that benefits from parallel processing and may need to be reprogrammed

Why might a designer choose a CPU over an FPGA according to the continuum of configurable computing?

CPUs are more flexible and easier to program for general purpose work

Which statement best describes the trade-off along the continuum of configurable computing?

Greater flexibility usually costs performance and power efficiency

What is Horner’s Rule primarily used for in computations mathematics?

To reduce the number of multiplications and additions in polynomial evaluation

How does Horner’s Rule simplify the computation of the polynomial y = Ax² + Bx + C?

By nesting operations to reduce the number of computations

Using Horner’s Rule, how many multiplications are required to evaluate y = Ax² + Bx + C?

2

If we evaluated y = Ax² + Bx + C using the standard method, how many additions and multiplications are needed?

2 additions, 3 multiplications

What is the advantage of using Horner’s Rule over the standard method for polynomial evaluation?

It requires fewer arithmetic operations

Why is Horner’s Rule particularly useful in embedded systems?

It reduces power consumption by minimizing the number of operations

How many additions and multiplications are required to evaluate the polynomial y = 2x³ + 3x² + 4x + 5

3 additions, 3 multiplications

Consider the polynomial y = 4x^4 + 3x³ + 2x² + x + 6. How many additions and multiplications are needed using Horner’s Rule?

4 additions, 4 multiplication

How many additions and multiplications are needed to evaluate y = 7x^6 + 5x³ + 3x + 9 using Horner’s Rule?

3 additions, 6 multiplications

How many additions and multiplications are required to evaluate the polynomial y = 10x² + 9x + 8 using Horner’s Rule?

2 additions, 2 multiplications

The MAX 10 on the DE10-Lite has 50,000 logic elements, and each logic array block holds 16 of them. How many logic array blocks does the device contain?

3,125

A combinational function of five inputs must be implemented on a MAX 10, whose logic element contains a four-input look-up table. What does the fitter have to do?

Use more than one logic element and combine their outputs

A combinational function of five inputs is implemented on a Xilinx 7-series device, whose slice contains six-input look-up tables. How many look-up tables does the function occupy?

One, because a six-input table covers a function of five variables

In the MAX 10 logic element diagram, a path labelled ‘register bypass’ carries the look-up table output past the flip-flop to the routing. What does this path make possible?

A combinational result reaches the routing without a clock cycle of latency

Embedded memory and embedded multipliers appear in the MAX 10 floorplan as full columns running through the logic array, rather than being scattered among the logic array blocks. What does the arrangement buy?

It shortens and regularises the routing to them, so nay nearby block reaches them predictably

A design is reported as using 90% of the devices logic elements but only 12% of its embedded multipliers. Which conclusion is best supported?

Capacity binds first, and moving arithmetic into the idle hardened blocks would free room

The Xilinx SLICEL diagram shows a carry chain entering at CIN and leaving at COUT, with dedicated wires rather than general routing. Why is a ripple carry adder built on that chain much fast than one built from ordinary look-up table logic?

Its own short fixed wiring avoids a switch relay at every bit position

A colleague proposes moving a finished, high-volume product form an FPGA to an ASIC. Which consideration most strongly argues against doing so?

The ASIC cannot be changed once fabricated, so any specification change means a new mask set

A signal must leave the FPGA on a bank running at 1.8V while the internal logic runs at a lower core voltage. Which resource handles that difference?

The I/O block int that bank

What does VHDL stand for?

Very High-speed Integrated Circuit Hardware Description Language

Which HDL was developed by Gateway Design Automation in 1984?

Verilog

What is the primary difference between synthesizable and non-synthesizable HDL code?

Synthesizable code can generate hardware, while non-synthesizable code cannot

Which HDL is known for being verbose and strongly typed?

VHDL

Which language is an extension of Verilog that supports object-oriented programming for verification purposes?

SystemVerilog

In the context of HDLs, what does the term ‘behavioral code’ refer to?

Code that describes the behavior of a system at a high level, showing input-output relationships

What is the first step in the FPGA design flow?

Design Entry

What does the ‘assign’ statement in SystemVerilog do?

It describes combinational logic

Which HDL is based on the Ada programming language?

VHDL

What type of modeling describes the connections between modules, similar to a motherboard connecting integrated circuits?

Structural modeling

What is the purpose of a testbench in HDL design?

To verify the functionality of the HDL design through simulation

Which operator is used in SystemVerilog for conditional assignments?

?

What type of HDL code describes the logical behavior of a circuit without specifying its structure?

Behavioral code

If the desired clock period is 10 ns and the WNS is 2 ns, what is the maximum FPGA clock frequency?

125 MHz

What is a desired clock period of 4 ns and a WNS of 2 ns, what is the maximum clock frequency that can be achieved?

500 MHz

If the maximum clock frequency is 125 MHz and the WNS is 3 ns, what is the desired clock period?

11 ns

Given a desired clock period of 8 ns and maximum clock frequency of 250 MHz, what is the WNS?

4 ns

What does a negative WNS (Worst Negative Slack) indicate about the timing of you FPGA design?

The design does not meet its timing requirements

Why must worst negative slack be taken into account when reporting how fast a design can be clocked?

It states how far the design met or missed its timing requirement

What should be the designer’s primary concern if the WNS is negative?

Meeting time contraints

A design’s reported maximum clock frequency is below the value the designer asked for. Which figure report states that directly?

A negative WNS

Which of the following is a potential consequence of ignoring a negative WNS in your FPGA design?

Timing violations leading to incorrect operation

How can a designer address a negative WNS to improve the maximum clock frequency?

Optimize the critical path to reduce its delay

What does a very small positive WNS close to zero suggest about your FPGA design?

The design is on the verge of failing its timing requirements

A designer has two versions of an FPGA design, specified with the same clock period in the .xdc file: Design A has a WNS of -1 ns and Design B has a WNS of 2 ns. Which design is more likely to run at a higher clock frequency without timing violations?

Design B

If an FPGA design’s WNS becomes more negative after adding additional logic, what does this suggest about the critical path?

The critical path has become longer

An FPGA design has a WNS of 0 ns. What would happen to the WNS if the clock period is decreased?

The WNS would decrease

What might be a reason to intentionally design with a small positive WNS?

To maximize performance while ensuring reliable operation

How does the concept of WNS help in evaluating the robustness of an FPGA design?

It identifies potential timing issues and the design’s margin against them

What does it mean if the reported slack differs between two runs on an unchanged source?

The tool makes different optimization choices on each run

A design’s slack is positive but close to zero. What does that imply about its tolerance to temperature and voltage variation?

The margin is narrow and may not survive extreme conditions

What impact might reducing the clock period have on a design with an initially positive WNS?

The WNS would decrease, possibly becoming negative

If an FPGA design’s WNS is negative after a synthesis run, what is one method to try to resolve this issue without altering the logic design itself?

Increase the desired clock period

A four-bit design has a required clock period of 10 ns. The timing report gives a WNS of -1.5 ns. What is the maximum clock signal frequency does the design actually support?

About 87 MHz

Which statement best captures the primary purpose of a hardware description language (HDL) such as SystemVerilog?

To specify the logic function so CAD tools can synthesize gates

SystemVerilog files typically use which extension?

.sv

In SystemVerilog, which of these may an NOT do?

start with a digit

Which set of values can the 4-state logic type represent?

0, 1, z, x

Which pair best distinguishes Verilog vs. SystemVerilog?

Verilog is a subset of SystemVerilog

Which statement about SystemVerilog case sensitivity is correct?

It is sensitive across identifiers

Which keyword terminates a module definition in SystemVerilog?

endmodule

Which of the following is true about whitespace in SystemVerilog source?

It is ignored except where it separates tokens