Sequential Logic and Latches

Vocabulary flashcards covering the fundamentals of sequential and combinational logic, NOR and NAND SR latches, state tables, and latch priority design.

Sequential logic

Logic whose output depends on the current inputs AND the history of inputs/outputs (stored state), requiring a memory element.

Combinational logic

Logic whose output depends ONLY on the current inputs, having no memory and no feedback.

General form of sequential logic

The four-part structure consisting of: external input $A \rightarrow$ combinational logic $\rightarrow$ external output $Z$; next state $Y$ goes into memory; memory feeds present state $y$ back into the logic.

Present state $y$ vs. Next state $Y$

$y$ is the internal input representing what memory holds now; $Y$ is the internal output representing what the logic computes to store next.

Asynchronous sequential circuit

A sequential circuit whose output updates as soon as the inputs change without a clock, such as the SR latch.

Synchronous sequential circuit

A sequential circuit whose output and stored state update only when a clock enables it.

Cross-coupled inverters

A bistable circuit that holds $D$ or $D'$ forever and serves as the basis of SRAM (cache), but cannot be written to because it has no inputs.

Three requirements of a latch / memory cell

1) Write a 1 regardless of contents; 2) write a 0 regardless of contents; 3) read the stored value without altering it (hold).

$Q(t)$ and $Q(t+1)$

$Q(t)$ (or $Q(\text{old})$) is the current state stored right now; $Q(t+1)$ (or $Q(\text{new})$) is the next value of $Q$ after inputs act on it.

NOR rule

Output is 1 only if ALL inputs are 0; any input of 1 forces the output to 0.

NAND rule

Output is 0 only if ALL inputs are 1; any input of 0 forces the output to 1.

NOR SR latch states

$S=0, R=0$ holds ($Q(t+1) = Q(t)$), $S=1, R=0$ sets ($Q=1, Q'=0$), $S=0, R=1$ resets ($Q=0, Q'=1$), and $S=1, R=1$ is invalid ($X$) forcing $Q=Q'=0$.

Active-LOW inputs

Inputs, such as those on a NAND latch, where the input that is 0 is the one actively doing the work.

NAND SR latch states

$S'=1, R'=1$ holds, $S'=0, R'=1$ sets ($Q=1$), $S'=1, R'=0$ resets ($Q=0$), and $S'=0, R'=0$ is invalid ($X$) forcing $Q=Q'=1$.

Hold input condition (NOR vs. NAND)

A NOR latch holds at $S=R=0$, whereas a NAND latch holds at $S'=R'=1$.

Input release rule (NOR latch)

When released from $S=R=1$, the input released last wins (e.g., if $R$ drops first then $S$ drops, $R$ dropping sets $Q=1$ and $S$ dropping holds it, making final $Q=1$).

State table row count

Given by the formula $2^{\text{number of inputs}}$, which counts the external inputs plus the current state if listed.

XNOR gate

A gate with a double curved back line and a bubble at the output, producing an output of 1 when both inputs are the same and 0 when they are different.

Priority gating (preventing $S=R=1$)

A design method of gating one input with the inverse of the other to prevent invalid states, such as $S = M$ and $R = K \times M'$ for set priority, or $R = H$ and $S = L \times H'$ for reset priority.

Alarm circuit (set priority)

A circuit where $M$ wins when $M=K=1$, with latch inputs $S = M$, $R = K \times M'$, and next state equation $L(t+1) = M + K' \times L(t)$.

Pump circuit (reset priority)

A circuit where $H$ wins when $L=H=1$, with latch inputs $R = H$, $S = L \times H'$, and next state equation $P(t+1) = H' \times (L + P(t))$.