Physical Journey from RTL

Mapping and Placement and Routing.

Name the stages from which RTL becomes FPGA hardware.

RTL module

Describes the behavior and state.

Elaboration

Resolves parameters and hierarchy

Synthesis

Translates logic into a technology-independent network and maps it to LUTs. registers, carry resources and other primitives.

Placement

Assigns legal physical sites

Routing

Allocates programmable wires and switches.

Functional Simulation

A software test that verifies the logical behavior of your HDL code against your design specifications using a testbench. It assumes zero physical delay for logic gates and wires, meaning it only checks what your circuit does, not how fast it runs on actual hardware.

Timing Closure

The process of optimizing a design's code and physical layout on the FPGA until every signal path meets its speed and clock requirements. It guarantees that data arrives at every flip-flop on time—without setup or hold violations—when accounting for real-world silicon and wire delays.

Mapped Netlist

The resulting hardware circuit description generated by synthesis, consisting strictly of target-specific FPGA primitives (such as LUTs, Flip-Flops, and BRAMs) and their logical interconnections, with no physical location data.

Floorplan

The physical 2D spatial blueprint of the FPGA silicon, created during the implementation phase, that assigns exact geographic regions or coordinates on the chip to the logic blocks in your mapped netlist.