EE457 Final Exam Review - VHDL and Lab Exercises

Comprehensive flashcards covering VHDL fundamentals, syntax, modeling styles, and hardware description concepts based on the EE457 course material.

VHDL

An IEEE industry standard high-level description language for both simulation & synthesis; stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.

Behavioral Modeling

A modeling style that describes the functionality of a circuit rather than its structure, with no specific hardware intent.

Structural Modeling

A modeling style that describes both the functionality and specific hardware structure of a circuit by calling out specific components.

Register Transfer Level (RTL)

A type of synthesizable behavioral modeling where hardware is implied or inferred for the purpose of synthesis.

Synthesis

The process of translating HDL code into a circuit and then optimizing the represented circuit.

Process

The basic unit of execution in VHDL used to describe behavior that synthesis tools translate into equivalent hardware structures.

LIBRARY clause

A symbolic name to a path/directory defined in the compiler tool that identifies a library name to be referenced.

USE clause

Specifies the specific package and object within a library to be used in the design.

STD_LOGIC_1164

An IEEE library package that defines $std\text{\_}logic$ types and related functions.

NUMERIC_STD

An IEEE library package used for arithmetic functions using standard logic vectors defined as $SIGNED$ and $UNSIGNED$ data types.

ENTITY

A mandatory VHDL design unit that defines the external interface (symbol) of a model, including generics and ports.

ARCHITECTURE

A mandatory VHDL design unit that defines the internal function or logic design (schematic/function) of the model.

CONFIGURATION

An optional design unit used to associate a specific architecture with an entity, often used in testbenches.

PACKAGE

An optional design unit that acts as a collection of information (declarations and bodies) to be shared between VHDL files.

Generic

Declarations used to pass parameter information into a model that must resolve to a constant during compilation.

Port

A signal list describing the inputs and outputs of an entity that acts as the external connections (pins).

Signal Modes

The direction of a signal; valid modes include $in$, $out$, $inout$ (bidirectional), and $buffer$ (output readable internally).

std_logic

A 9-value logic system including $'1'$ (High), $'0'$ (Low), $'X'$ (Unknown), $'Z'$ (Tri-state), and $'-'$ (Don't Care).

Concatenation Operator ($\&$)

The VHDL operator used to join multiple signals or vectors together into one.

Constant

A VHDL data object whose value is assigned at declaration and cannot be changed during simulation or after compilation.

Variable

A VHDL object declared inside a process or subprogram that is updated immediately upon assignment ($:=$) and provides temporary storage.

Signal

A VHDL object that represents internal wiring ($<=$) and is updated at the end of the current delta cycle rather than immediately.

Conditional Signal Assignment

A concurrent assignment using the $WHEN\text{-}ELSE$ format.

Selected Signal Assignment

A concurrent assignment using the $WITH\text{-}SELECT\text{-}WHEN$ format where all conditions must be considered.

Sensitivity List

A list of signals that trigger the execution of an explicit process when an event (transition) occurs on any of them.

WAIT statement

A statement that pauses process execution until a condition is satisfied; types include $WAIT\,ON$, $WAIT\,UNTIL$, and $WAIT\,FOR$.

Function

A VHDL subprogram that performs sequential computations, returns exactly one value, and cannot contain $WAIT$ statements.

Component

A module declaration that acts as a placeholder representing a subsystem (entity/architecture pair) in a hierarchical design.

Finite State Machine (FSM)

A logic design that transitions between defined states based on inputs, typically described in VHDL using an enumerated data type for states.

rising_edge(clk)

An IEEE function that specifies a signal transition must go specifically from $0$ to $1$ to evaluate as true.