Software Engineering, Computer Systems, Digital Systems & Computer Networks

Comprehensive vocabulary flashcards covering Software Engineering, Computer Systems, Digital Systems, and Computer Networks review material for the FE Electrical and Computer CBT Exam.

Algorithm

A procedure or formula for solving a problem, based on conducting a sequence of specified actions.

Flow Chart Symbols

Diagrammatic symbols used to illustrate an algorithm or process: a rectangle represents a process operation, an oval represents a start or stop point, a diamond represents a decision point, a parallelogram represents data input/output (I/O), a wavy-bottom rectangle represents a document, and a cylinder represents a database.

Structured Programming

A programming paradigm aimed at improving the clarity, quality, and development time of computer programs by making extensive use of the three fundamental control flow constructs: sequencing, selection (if/then/else), and repetition (while/for).

While Loop vs. Do-While Loop

A while loop evaluates its Boolean exit condition before executing an iteration (meaning the body may execute zero times), whereas a do-while loop evaluates its exit condition after an iteration, guaranteeing that the body executes at least once.

Big-O Notation

A mathematical metric used in software engineering to describe the scalability and efficiency of an algorithm by comparing execution time growth rates as the number of processed elements $n$ approaches infinity.

Bubble Sort (Sink Sort)

A sorting algorithm with $O(n^2)$ worst-case complexity that compares each pair of neighboring items and swaps them if they are in the wrong order, causing the largest unsorted elements to settle in order at the end of the array after each pass.

Insertion Sort

A sorting algorithm with $O(n^2)$ worst-case complexity that iterates by consuming one input element at a time and placing it into its correct position within an expanding, sorted output list.

Merge Sort

A divide-and-conquer sorting algorithm with $O(n \log(n))$ complexity that recursively splits an input array into two halves until single elements remain, and then merges the sorted halves together.

Max-Heap

A full binary tree where each node has at most two children and every node has a value smaller than or equal to its parent, positioning the maximum value at the root.

Quick Sort

A divide-and-conquer sorting algorithm that partitions an array around a pivot value ($A \le \text{pivot} \le B$); it has a worst-case complexity of $O(n^2)$ but achieves an efficient average performance of $O(n \log(n))$.

Binary Search

A search algorithm with $O(\log(n))$ complexity that operates on an ordered (sorted) array by halving the search space at each step through middle-element bisection.

Hash Table

A data structure that uses a hashing function to map search keys to memory array indices (buckets) to store and locate data records in $O(1)$ average time.

Linked List

A dynamic data structure consisting of a sequence of elements where each element contains a pointer link to the next element, enabling $O(1)$ insertions and deletions when the location is known, but requiring $O(n)$ sequential traversal to find an element.

Double Linked List

A dynamic sequential data structure where each node stores a data item along with two pointers: one linking to the previous node and another linking to the next node, allowing bidirectional navigation.

Queue

A First-In, First-Out (FIFO) data structure in which items are added (pushed) exclusively at the tail and removed (popped) exclusively from the head.

Stack

A Last-In, First-Out (LIFO) data collection where element insertion (push) and element deletion (pop) are restricted to the head (top) of the stack.

Map

A data structure that stores distinct keys paired with values where each unique key maps to a single value, typically offering constant-time access via key hashing.

Set

A data structure that stores elements in no particular order and guarantees that no values are duplicated.

Breadth-First Search (BFS)

A graph traversal strategy implemented using a queue data structure that visits all immediate neighbor nodes connected to a parent node before advancing to the next level of child nodes.

Depth-First Search (DFS)

A graph traversal technique that visits the first unvisited connected node along a path until no further connected nodes are available, and then backtracks to explore alternate branches.

Pre-order Traversal

A tree traversal procedure that first visits the root node, then recursively traverses the left subtree, and finally traverses the right subtree.

In-order Traversal

A binary tree traversal procedure that traverses the left subtree, visits the root node, and then traverses the right subtree.

Post-order Traversal

A tree traversal procedure that recursively traverses the left subtree, traverses the right subtree, and visits the root node last.

Pointer

A reference variable whose literal value is the memory address of an object; retrieving the object located at that address is known as dereferencing.

Recursion

A software implementation technique where a function calls itself repeatedly on diminishing subsets of data until reaching a defined termination condition.

White-Box Testing

A software testing method where the internal source code is visible to and reviewed directly by the tester, typically conducted by the designer.

Black-Box Testing

A software validation method where functionality is evaluated from external inputs and outputs without knowledge or inspection of the underlying source code.

Waterfall Model

A sequential software development process flow consisting of Requirements, Design, Implementation, Verification, and Maintenance, where preceding steps cannot be repeated.

V-Model

A software development lifecycle model pairing each project definition phase (concept of operations, requirements, detailed design) directly with a corresponding testing and integration phase (unit testing, system verification, operation and maintenance).

McCabe's Cyclomatic Complexity

A software metric quantifying the complexity of a program graph and determining the minimum number of tests needed to traverse all control paths, calculated by $c = e - n + 2$ where $e$ is edges and $n$ is nodes.

Arithmetic Logic Unit (ALU)

A core component of the central processing unit (CPU) that executes all basic arithmetic calculations and Boolean logic operations.

RISC vs. CISC

Architectural classification where Reduced Instruction Set Computers (RISC) execute smaller, simpler instructions directly in hardware, whereas Complex Instruction Set Computers (CISC) use microcode conversion to decompose complex machine instructions into executable microinstructions.

Harvard Architecture

A computer architecture design featuring physically separate storage spaces and independent bus signal paths for instructions and data, enabling the CPU to read an instruction and perform a data memory access concurrently.

Von Neumann Architecture

A computer architecture where both program instructions and data share the same physical memory and bus path, preventing simultaneous instruction fetching and data read/write operations.

Direct Addressing Mode

A processor memory addressing mode in which the instruction's address field directly specifies the memory address where the operand data is stored.

Indirect Addressing Mode

A memory addressing mode in which the instruction's address field points to a memory location that contains the effective pointer/address of the operand.

Register Indirect Addressing Mode

An addressing mode where the instruction designates a CPU register that contains the memory address of the operand.

Displacement (Indexed) Addressing Mode

An addressing scheme combining direct and register indirect modes where the effective operand address is computed by adding an offset displacement to a base address held in a register.

Instruction Pipelining

A microarchitectural technique where instruction execution is partitioned into sequential stages (such as IF, ID, EX, MEM, WB) running simultaneously on different instructions to boost overall instruction throughput.

Pipeline Hazard

An event that disrupts steady pipeline execution and wastes clock cycles (stalls), categorized into data hazards (an instruction depends on unready data) and control hazards (branching or interrupts requiring pipeline flushes).

Set-Associative Cache

A cache memory structure of size $C = S \times A \times B$ where memory lines map to a specific set determined by index bits ($\log_2(S)$), and within that set can occupy any of $A$ ways, verified using tag comparators.

Write-Through vs. Write-Back

Cache write-through updates both cache memory and main backing memory simultaneously upon every write, whereas write-back writes exclusively to cache memory and defers writing to main memory until the line is evicted.

Static RAM (SRAM) vs. Dynamic RAM (DRAM)

SRAM uses multi-transistor latch circuits to store bits statically without refreshing (making it fast and expensive for caches), whereas DRAM stores bits on capacitive charges requiring periodic refreshing thousands of times per second (making it cheap and dense for main memory).

Hard Disk Platter Architecture

Magnetic disk storage layout where rotating platters are subdivided into concentric circular tracks, each track is segmented into sectors of fixed size, and multiple sectors form clusters.

Radix (Base)

The total number of unique digit symbols, including zero, utilized in a positional numbering system (for instance, radix 10 for decimal, radix 2 for binary, radix 8 for octal, and radix 16 for hexadecimal).

Two's Complement

A mathematical representation for signed binary numbers where a negative integer is formed by inverting all bits of its positive counterpart (one's complement) and adding 1.

DeMorgan's Laws

Foundational Boolean theorems that define equivalent inverted logic operations: $\overline{A + B} = \overline{A} \cdot \overline{B}$ and $\overline{A \cdot B} = \overline{A} + \overline{B}$.

Minterm ($m_i$)

A product (AND) term of $n$ Boolean variables in which each variable appears once in either uncomplemented or complemented form, producing an output of 1 for that specific input combination.

Maxterm ($M_i$)

A sum (OR) term of $n$ Boolean variables in which each variable appears once in either complemented or uncomplemented form, producing an output of 0 for that specific input combination.

Karnaugh Map (K-Map)

A graphical minimization grid where adjacent squares differ by exactly one variable via Gray code, enabling the grouping of rectangular powers-of-two 1s or 0s into minimal Boolean algebraic expressions.

Don't Care Condition ($X$)

An unspecified input combination in a truth table or K-map whose resulting output value has no operational consequence, allowing it to be grouped freely as either a 0 or a 1 to maximize logic simplification.

D Latch

A level-sensitive digital storage circuit that samples input $D$ and reflects it at output $Q$ while enable ($En$) is high, and holds the last state when $En$ drops to low.

JK Flip-Flop

An edge-triggered bistable multivibrator whose operation follows $Q(t+1) = J\overline{Q} + \overline{K}Q$; setting $J=1, K=0$ sets the output, $J=0, K=1$ resets it, and $J=1, K=1$ toggles (complements) the output.

Ripple (Asynchronous) Counter

A cascaded counter circuit in which the clock pulse drives only the initial flip-flop, while each subsequent flip-flop is clocked by the transition of the output of the preceding stage.

Synchronous Counter

A counter circuit in which all constituent flip-flops are connected to a single common clock source and transition their state bits at the exact same instant.

Decade Counter

A digital counter designed to count through ten distinct decimal states (0 through 9, binary 0000 to 1001) before resetting to zero.

Combinational Logic Circuit

A digital circuit constructed from logic gates whose instantaneous output values depend entirely and solely on present input values, containing no memory or feedback paths.

Half Adder

A combinational circuit that adds two single-bit binary inputs $x$ and $y$, yielding a Sum output ($S = x \oplus y$) and a Carry output ($C = xy$).

Full Adder

A combinational arithmetic circuit that sums three binary bits ($A$, $B$, and Carry-in $C_{\text{in}}$) to produce a Sum ($S = A \oplus B \oplus C_{\text{in}}$) and a Carry-out ($C_{\text{out}} = AB + BC_{\text{in}} + AC_{\text{in}}$).

Decoder

A combinational logic device that converts an $n$-bit encoded binary input into a maximum of $2^n$ individual output lines, asserting exactly one output line corresponding to the input code.

Priority Encoder

A combinational circuit that converts several input lines into an encoded binary output, giving operational precedence to the highest-order active input line when multiple inputs are asserted.

Multiplexer (MUX)

A combinational logic switch that accepts $2^n$ data inputs and uses $n$ select lines to direct data from one chosen input channel to a single output line.

Programmable Logic Device (PLD)

A general-purpose integrated circuit with uncommitted logic gates and programmable internal switches or fuses that can be configured by the user to implement arbitrary digital functions.

Static Hazard

A transient flaw in combinational circuits where an output momentarily pulses to an incorrect state (0 in a Static-1 hazard, or 1 in a Static-0 hazard) before settling, caused by unequal gate propagation delays when a single input transitions.

Dynamic Hazard

A hazard condition in multi-level combinational circuits where an output changes multiple times (e.g., $1 \rightarrow 0 \rightarrow 1 \rightarrow 0$) before resting at its correct value in response to a single input transition.

Critical Race Condition

A timing defect in asynchronous sequential circuits where two or more state variables change simultaneously, and unequal transmission delays cause the final stable state to depend uncontrollably on which variable changes first.

Ring Counter

A circular shift register counter where the output of the final stage is connected directly back to the data input of the first stage, circulating an isolated single bit through $n$ distinct states.

Johnson Counter

A twisted-ring counter where the inverted output ($\overline{Q}$) of the last shift register stage is fed back into the input of the first stage, producing a circulating sequence of $2k$ states for a $k$-bit register.

Circuit Switching

A telecommunications network method where a physical or virtual communication circuit is pre-established and dedicated between sender and receiver prior to transmission, providing guaranteed bandwidth but slow setup.

Packet Switching

A communication methodology where messages are segmented into individually addressed packets that traverse available network paths dynamically without pre-allocated circuits, maximizing transmission efficiency.

Network Switch

A Layer 2 (Data Link) local networking device that forwards data frames specifically to destination hosts based on hardware MAC addresses, supporting collision-free full-duplex traffic.

Network Router

A Layer 3 (Network) internetworking device that inspects logical destination IP addresses and routes data packets across disparate subnets and over the Internet.

Network Hub

A basic Layer 1 physical device that repeats and broadcasts incoming data packets blindly across all connected ports in half-duplex mode.

Network Topologies

The structural layout configurations of devices in a network, including Point-to-Point, Bus, Star, Ring, Mesh, and Tree geometries.

Token Ring Topology

A deterministic local area network topology where a small electronic token frame circulates between stations; only the station holding the token is permitted to transmit data, eliminating packet collisions.

Full Mesh Topology

A highly resilient, self-healing network topology where every node is directly connected to every other node via dedicated links, requiring $\frac{N(N-1)}{2}$ physical links for $N$ nodes.

Dynamic Host Configuration Protocol (DHCP)

A network protocol that allows a router or server to automatically assign IP addresses, subnet masks, and configuration settings to client devices joining a local network.

Address Resolution Protocol (ARP)

A local area communication protocol used to discover and map an unknown physical MAC address corresponding to a known destination IP address.

Propagation Delay ($d_{\text{prop}}$) vs. Transmission Delay ($d_{\text{trans}}$)

Propagation delay ($d_{\text{prop}} = \frac{d}{s}$) is the time required for a signal wave to travel a physical distance $d$ at propagation velocity $s$, while transmission delay ($d_{\text{trans}} = \frac{L}{R}$) is the time needed to push a packet of length $L$ bits onto a link of transmission rate $R$.

OSI vs. TCP/IP Models

Layered networking frameworks comparing the 7-layer OSI model (Physical, Data Link, Network, Transport, Session, Presentation, Application) to the 4-layer TCP/IP architectural suite (Network Access, Internet, Transport, Application).

Transmission Control Protocol (TCP)

A reliable, connection-oriented Transport Layer protocol that provides sequenced, error-checked, and flow-controlled data transmission using sliding windows and acknowledgments.

User Datagram Protocol (UDP)

A lightweight, connectionless Transport Layer protocol that transmits datagrams without establishing a virtual circuit, providing best-effort delivery without acknowledgments or flow control.

Internet Control Message Protocol (ICMP)

A network-layer diagnostic and reporting protocol utilized by operational utilities such as ping and traceroute using Time-to-Live (TTL) packet counters.

Automatic Repeat Request (ARQ)

A reliable data link protocol mechanism utilizing positive acknowledgments (ACK), negative acknowledgments (NAK), sequence numbers, and timeouts to guarantee delivery over imperfect communication channels.

Sliding Window Protocol

A transport data transmission protocol that permits the sender to dispatch multiple sequence-numbered frames (window size) before requiring acknowledgment, dynamically matching link throughput to network conditions.

Firewall

A network security appliance or software service that filters, inspects, and controls incoming and outgoing packet traffic based on an established set of security rules.

Port Scanning

The reconnaissance process of probing a range of TCP and UDP ports on a server or host to identify active listening services and discover accessible communication pathways.

Security Triad (CIA Triad)

The three foundational pillars of cybersecurity: Confidentiality (restricting access to authorized users), Integrity (ensuring data is accurate and untampered), and Availability (guaranteeing reliable, timely service access).

Penetration Testing Phases

The structured five-step lifecycle of an authorized cyberattack simulation: Reconnaissance, Scanning, Gaining Access, Maintaining Access (creating persistence/backdoors), and Covering Tracks.

Fundamentals of Engineering (FE) CBT Exam

A 6-hour, closed-book computer-based examination developed and administered by NCEES containing 110 questions that assesses comprehensive engineering knowledge across standardized specification categories.

NCEES Model Law and Model Rules

Standardized governance publications authored by the National Council of Examiners for Engineering and Surveying providing codes of ethics, professional conduct standards, and baseline legal definitions for engineering licensure.