Unit 5: Input-Output and Memory Organization

Vocabulary practice flashcards covering Input-Output interfaces, data transfer modes, priority interrupts, DMA, and memory hierarchies including RAM, ROM, associative memory, and cache mapping schemes.

Input-Output (I/O) Interface

Special hardware placed between the CPU/internal storage and external I/O devices to supervise, synchronize, and translate data transfers between electronic CPU/memory circuits and slower electromechanical/electromagnetic peripherals.

Functions of an I/O Interface

Performs data conversion (such as digital to analog and serial to parallel), synchronization (matching the operating speeds of the CPU and peripherals), and device selection (allowing the CPU to select the required device).

I/O Bus Lines

The three sets of lines within an I/O bus: Data lines that carry data, Address lines that identify the required device, and Control lines that carry commands and control information.

I/O Command Types

Four function codes sent through control lines: Control command (directs peripheral operations), Status command (tests device condition/errors), Data output command (transfers data from processor to peripheral), and Data input command (transfers data from peripheral to processor).

I/O Processor (IOP)

An independent processor, also called a data channel, that provides an autonomous communication pathway between external I/O devices and internal memory via dedicated buses.

Isolated I/O

An I/O configuration where memory and I/O devices have separate address spaces, use distinct control lines (Memory Read/Write vs. I/O Read/Write), and require specialized input/output instructions, preventing the reduction of memory address space.

Memory-Mapped I/O

An I/O configuration where I/O interface registers share the same address space as memory, share a single set of Read/Write control signals, and are accessed using standard memory instructions (e.g., load and store), which reduces available memory addresses.

Interface Registers (Port A, Port B, Control, Status)

Registers within an interface unit where Port A and Port B transfer I/O data, the Control register receives configuration commands from the CPU, and the Status register records device condition flags and error states.

Chip Select ($\text{CS}$) and Register Select ($\text{RS1}, \text{RS0}$)

Interface control inputs where $\text{CS} = 1$ enables the interface unit, and $\text{RS1}$ and $\text{RS0}$ select one of the four internal registers: $00$ for Port A, $01$ for Port B, $10$ for Control register, and $11$ for Status register ($\text{CS} = 0$ puts the data bus in high-impedance).

Asynchronous Data Transfer

Data transfer between two independent units that use separate internal clocks with no common timing reference, requiring control signals such as strobes or handshaking to coordinate transfers.

Strobe Method

An asynchronous transfer method where a single control pulse is transmitted by one unit (either source or destination) to indicate to the other unit when data is available or requested on the bus, without an acknowledgment signal.

Handshaking Method

An asynchronous data-transfer technique that uses two control signals—a request/validation signal from the initiator and a reply/acknowledgement signal from the receiver—to guarantee data is accepted before concluding the transfer.

Source-Initiated Handshaking

A handshaking sequence where the source places data on the bus and asserts Data Valid; the destination accepts the data and asserts Data Accepted; the source disables Data Valid, and the destination disables Data Accepted.

Destination-Initiated Handshaking

A handshaking sequence where the destination enables Ready for Data; the source places data on the bus and enables Data Valid; the destination accepts data and disables Ready for Data; and the source disables Data Valid.

Asynchronous Serial Transfer

A transfer mode that transmits data one bit at a time over a single line kept at an idle state of $1$, formatting each character with a start bit ($0$), data bits, and one or more stop bits ($1$) to maintain synchronization.

Baud Rate

The rate of serial data transmission expressed in bits per second ($\text{bits/s}$); for example, transmitting $10$ characters per second at $11$ bits per character equals $110\,\text{bits/s}$.

UART (Universal Asynchronous Receiver-Transmitter)

A communication circuit that converts parallel data from the computer into serial data for transmission, and converts incoming serial data back into parallel data for the computer.

FIFO (First-In, First-Out) Buffer

A temporary storage unit consisting of registers and control flip-flops that stores incoming data and outputs it in the exact order of arrival, enabling smooth communication between devices operating at different speeds.

Ripple-Through Operation

The automatic movement of data in a FIFO buffer from one register to the next empty adjacent register when its associated control flip-flop indicates that the succeeding stage is empty ($F = 0$).

Program-Controlled I/O

A data transfer mode in which the CPU continuously executes a program polling loop to monitor an interface flag bit until the device is ready, keeping the processor needlessly busy during slow transfers.

Interrupt-Initiated I/O

A transfer mode where the CPU executes normal programs while the interface monitors the peripheral; when ready, the interface issues an interrupt request, prompting the CPU to save its context and branch to an I/O service routine.

Vectored vs Nonvectored Interrupt

In a nonvectored interrupt, the CPU branches to a fixed, predefined memory address; in a vectored interrupt, the interrupting source supplies the branch information (interrupt vector) directly to the CPU.

Priority Interrupt

A system that arbitrates between multiple simultaneous interrupt requests to determine which device is serviced first, giving high-speed devices (like magnetic disks) precedence over slower ones (like keyboards).

Polling (Software Priority Interrupt)

A software-based priority method where the CPU polls interrupt sources in a sequential order defined by code; it requires minimal hardware and is flexible, but operates very slowly.

Daisy-Chain Priority Interrupt

A serial hardware priority mechanism where all devices share a common interrupt request line and an acknowledge line ($\text{INTACK}$) is passed through devices in series; the requesting device physically closest to the CPU intercepts the signal and places its vector address on the bus.

Priority In ($\text{PI}$) and Priority Out ($\text{PO}$)

Signals in a daisy-chain module where $\text{PI} = 1$ indicates the acknowledge signal has arrived; if the device has a pending request ($\text{RF} = 1$), it enables its vector address and sets $\text{PO} = 0$; if $\text{RF} = 0$, it passes the signal downstream by setting $\text{PO} = 1$.

Parallel Priority Interrupt

A hardware scheme that uses an Interrupt Register, a Mask Register, and a Priority Encoder to simultaneously evaluate multiple interrupt request lines and immediately output the corresponding vector address.

Interrupt Enable ($\text{IEN}$) and Interrupt Status ($\text{IST}$)

Flip-flops in an interrupt system where $\text{IEN}$ is set or cleared by program instructions ($\text{ION}$ or $\text{IOF}$), and $\text{IST}$ is set to $1$ when an unmasked interrupt request occurs; both must be $1$ to enter an interrupt cycle.

Interrupt Cycle Microoperations

The hardware sequence executed when an interrupt is acknowledged: $SP \leftarrow SP - 1$, $M[SP] \leftarrow PC$, $INTACK \leftarrow 1$, $PC \leftarrow VAD$, and $IEN \leftarrow 0$.

Direct Memory Access (DMA)

A data transfer technique where an external interface controller transfers entire blocks of data directly between memory and high-speed peripherals via the system buses without continuous CPU intervention.

DMA Burst Transfer

A DMA transfer mode where the DMA controller maintains mastery of the memory buses and continuously transfers an entire block of memory words in one uninterrupted operation.

Cycle Stealing

A DMA transfer mode where the DMA controller takes control of the memory buses to transfer exactly one word at a time, momentarily delaying the CPU for one memory cycle before releasing the buses.

DMA Bus Signals ($\text{BR}$ and $\text{BG}$)

Control lines between the CPU and DMA controller where Bus Request ($\text{BR}$) is asserted by DMA to request bus control, and Bus Grant ($\text{BG}$) is asserted by the CPU to relinquish the buses.

DMA Controller Registers

Three internal registers: the Address Register (stores and increments the memory location), the Word Count Register (holds and decrements the number of words to transfer until zero), and the Control Register (specifies read/write transfer mode).

Memory Word

The fixed number of bits that can be stored or accessed as a single unit at a specific memory location; for example, in a $4\text{K} \times 8$ memory, each memory word is $8$ bits ($1$ byte).

Memory Hierarchy

An architectural structure organizing memory from fast, small, expensive types (registers, cache) to slower, larger, cheaper storage (main memory, magnetic disk, magnetic tape) to maximize access speed while minimizing overall system cost.

Static RAM (SRAM)

A form of random-access memory constructed of internal flip-flop circuits that retains stored bits without periodic refreshing as long as power is supplied, commonly used in cache memory.

Dynamic RAM (DRAM)

A form of random-access memory that stores data bits as electrical charges on capacitors inside MOS transistors, requiring periodic refreshing because the charge gradually leaks away; commonly used for main memory.

Bootstrap Loader

A startup program permanently stored in ROM that executes when the computer is powered on, setting the Program Counter to load the operating system from disk into main RAM and transferring control to it.

Memory Address Map

A tabular or pictorial representation assigning specific ranges of hexadecimal and binary address bus lines to individual RAM and ROM chips within a microcomputer system.

Seek Time and Transfer Time

Components of auxiliary memory access time: seek time is the duration required to position the read/write head over the desired track, and transfer time is the time required to read or write data once positioned.

Magnetic Disk Tracks and Sectors

The structural layout of a circular magnetic disk: concentric circular rings where bits are recorded are tracks, and angular slices of tracks are sectors, which represent the minimum unit of data transfer.

Associative Memory (Content Addressable Memory / CAM)

A memory unit accessed simultaneously and in parallel based on data content rather than a specific address; it identifies matching words across all stored locations concurrently.

Argument Register ($A$) and Key Register ($K$)

Registers in an associative memory of $n$ bits per word where register $A$ holds the search bit pattern, and mask register $K$ specifies which bit positions are compared (bits with $1$s in $K$ are compared; bits with $0$s are masked).

Match Register ($M$)

An $m$-bit register in an associative memory containing one bit per memory word; a bit is set to $1$ whenever its corresponding stored word matches the unmasked bits of the Argument Register.

Cache Memory

A very fast, small semiconductor memory situated between the CPU and main memory to hold frequently used data and instructions, bridging the operational speed gap.

Locality of Reference

The computational principle that memory references over a period of time tend to cluster within small localized regions, consisting of Temporal Locality (recently referenced items being used again soon) and Spatial Locality (nearby locations being referenced soon).

Cache Hit and Cache Miss

A cache hit occurs when the CPU references memory and finds the requested word in cache; a cache miss occurs when the word is absent from cache, requiring an access to main memory.

Hit Ratio

A measure of cache memory performance defined by the formula $\text{Hit Ratio} = \frac{\text{Number of Hits}}{\text{Number of Hits} + \text{Number of Misses}}$.

Associative Mapping (Cache)

A cache mapping method in which any memory block can reside in any cache location; the cache mapping table is implemented in associative memory storing both the 15-bit address and 12-bit data.

Direct Mapping (Cache)

A cache organization where each main memory block maps to only one specific cache line determined by its index field; the CPU address is partitioned into an index field to address cache and a tag field to verify a match.

Set-Associative Mapping

A hybrid mapping technique dividing cache into sets of lines; the index field identifies the set, and the block can be placed in any line within that set, comparing tag bits across all lines in parallel.

Write-Through Policy

A cache write strategy in which every CPU write operation updates main memory immediately; on a hit, both cache and main memory are updated, and on a miss, data is written directly to main memory.

Write-Back Policy (Copy-Back)

A cache write policy where data is updated exclusively in the cache on a write hit, and main memory is only updated later when the modified (dirty) cache block is evicted.