Moderni architecture

Temporal Locality

Temporal locality is the principle stating that if a memory location is referenced once, it will tend to be referenced again soon^[1]. Caching systems exploit this behavior by retaining recently accessed instructions and data in small, high-speed SRAM levels close to the processor core^[2]. This behavior is common in loops, frequently accessed variables, and function calls^[1].

Spatial Locality

Spatial locality is the principle stating that if a memory item is referenced, items whose memory addresses are nearby will tend to be referenced soon^[1]. Hardware memory systems exploit this principle by copying an entire contiguous multi-byte block of data from main memory into the cache whenever a miss occurs^[2]. This design ensures that sequential instruction execution and array traversals achieve high cache hit rates^[1][2].

Cache Hit vs. Cache Miss

A cache hit occurs when requested data is present in the cache, allowing data transfer directly between the cache and processor without utilizing the system bus^[2]. A cache miss occurs when the requested address is not in the cache, requiring the activation of memory buffers to access the system bus^[2]. Fetching data across the system bus introduces an additional access delay known as the miss penalty, which causes pipeline stall cycles^[2].

Write-Through vs. Write-Back

Under a write-through policy, every write operation updates both the cache block and the lower-level main memory simultaneously, which slows down write operations^[3]. Under a write-back policy, data is written exclusively to the cache block, updating the lower-level memory only when that modified block is evicted and replaced^[3]. Write-back reduces bus traffic, but hardware must implement coherency mechanisms to prevent multiprocessors and I/O devices from reading stale data^[3].

The Three Miss Categories (The 3 Cs)

Compulsory misses occur on the very first access to a block, which cannot be in the cache even if capacity were infinite^[4]. Capacity misses happen when the cache is not large enough to hold all blocks required during program execution, forcing blocks to be discarded and retrieved later^[4]. Conflict misses occur in direct-mapped or set-associative caches when multiple active memory blocks map to the exact same set and overwrite each other^[4].

Control Hazard

A control hazard occurs when a conditional or unconditional branch instruction is executed and the address of the next instruction to fetch is not yet known^[5]. The processor must evaluate condition flags and calculate the target address before knowing whether the branch is taken or falls through^[5]. Control hazards can impose a severe performance penalty on pipelined and multiple-issue processors by stalling instruction fetch^[5][6].

Structural Hazard & Pipeline Bubble

A structural hazard is a hardware resource conflict that arises when a functional unit is shared across multiple pipeline stages or is not fully pipelined^[7]. The processor resolves this conflict by stalling the pipeline for one or more clock cycles^[7]. This inserted stall is termed a pipeline bubble because it propagates through the pipeline stages occupying hardware space without performing useful work^[7].

Data Hazard & Forwarding

A data hazard arises when an instruction depends on the result of an earlier instruction that has not yet completed execution and write-back^[5][8]. When a load instruction produces data in the memory (MEM) stage that an immediately following instruction requires in the execute (EX) stage, a stall cycle must be inserted^[5]. In other arithmetic dependencies, hardware forwarding routes results directly between pipeline registers to bypass register file delays^[5][8].

Branch Target Buffer (BTB)

A Branch Target Buffer is an on-chip cache that stores the target address of branches alongside branch predictions^[9]. It is indexed using the instruction Program Counter (PC) during the fetch stage, allowing the processor to determine the branch target even before instruction decoding begins^[9]. If a match is found and predicted taken, the processor immediately redirects instruction fetch to the predicted PC without incurring stall cycles^[9].

Dynamic Branch Prediction

Dynamic branch prediction improves execution accuracy by tracking and learning the historical behavior of individual branch instructions at runtime^[6]. It utilizes a Branch History Table (BHT) indexed by branch address to store whether a branch was taken or not taken during recent executions^[6][10]. This approach prevents recurring misprediction penalties caused by static prediction schemes on complex multiple-issue processors^[6].

Interrupt Latency

Interrupt latency is defined as the elapsed time between the hardware assertion of an Interrupt Request (IRQ) signal and the start of Interrupt Service Routine (ISR) execution^[11]. Context saving—pushing processor registers to memory—adds latency overhead at both the entry and exit of the interrupt handler^[11]. Minimizing this latency is critical for deterministic response times in real-time embedded systems

Hardware Exception Stacking

When an interrupt occurs, the ARM Cortex-M3 hardware automatically pushes eight core registers—r0–r3, r12, LR, PC, and xPSR—onto the active stack^[11]. This automatic stacking preserves caller-saved registers defined by the ARM Architecture Procedure Call Standard without requiring software instructions^[11][13]. Because context saving is handled by hardware, standard C functions can serve directly as interrupt service routines without custom compiler attributes^[12][13].

EXC_RETURN

Upon interrupt entry and register stacking, the Cortex-M3 hardware loads a reserved bit pattern called EXC_RETURN into the Link Register (LR)^[14]. When the ISR completes and executes a branch exchange instruction (BX LR), loading this special pattern into the PC instructs the core to initiate the hardware exception return sequence^[14]. The processor restores the stacked registers from memory, provided the CPU is running in privileged Handler Mode^[14].

Tail Chaining

Tail chaining is an ARM hardware optimization that activates when an ISR completes and another interrupt of equal or lower priority is pending^[15][16]. Instead of executing an unstacking sequence to restore context only to immediately restack registers for the next interrupt, the CPU skips context restoration and jumps directly to the pending ISR^[15]. This exploits the valid saved context already present on the stack, drastically reducing back-to-back interrupt latency^[15][16].

Late Arrival

Late arrival occurs when a higher-priority interrupt request is asserted while the processor is already in the middle of stacking registers for a lower-priority interrupt^[15]. Rather than aborting or repeating the stacking process, the processor finishes the current register stacking and immediately executes the higher-priority ISR^[15]. This hardware optimization prevents the high-priority handler from waiting for the low-priority routine without adding redundant stacking overhead^[15].

Main Stack Pointer (MSP) vs. Process Stack Pointer (PSP)

The ARM Cortex-M3 implements two banked stack pointers mapped to register r13^[11][13]. The Main Stack Pointer (MSP) is typically used by the operating system kernel and all interrupt service routines^[13]. The Process Stack Pointer (PSP) is assigned to user application tasks, isolating user memory to prevent task failures from corrupting kernel stack frames^[13].

Cache Coherency & Bus Snooping

In Symmetric Multiprocessing (SMP) systems where processors share a common system bus, multiple private caches can hold copies of the same main memory block^[17]. If processors update local caches independently, they develop an inconsistent, non-coherent view of main memory^[17]. To resolve this, each cache controller implements bus snooping, continuously monitoring shared bus traffic to detect updates or invalidations to shared blocks^[17].

MESI Protocol

The MESI protocol maintains hardware cache coherency by enforcing a single-writer/multiple-reader invariant across four cache block states^[18][19]. A block can be Modified (dirty, exclusive to this cache, memory out of date), Exclusive (clean, exclusive, memory up to date), Shared (clean, identical to memory, replicated across caches), or Invalid (stale, unusable data)^[19][20]. When a core modifies a shared block, it broadcasts an invalidation across the bus so other caches transition their copies to Invalid^[18][20].

Arithmetic Logic Unit (ALU) & Datapath

The ALU is a core functional unit within the processor datapath that performs integer arithmetic and bitwise logic operations specified by an instruction's opcode^[21][22]. The datapath comprises functional units like ALUs, multipliers, and register files that perform data processing operations^[21]. The control unit regulates interactions between the datapath, registers, and memory by decoding instructions and generating internal control signals^[8][21].

SIMD (Single Instruction, Multiple Data)

SIMD is an architectural computing classification where a single instruction stream operates simultaneously across multiple distinct data elements in parallel^[22]. Modern architectures implement dedicated execution hardware, such as the ARM Cortex-A8 10-stage NEON pipeline, to process packed vector arrays^[22]. This parallel model accelerates data-intensive workloads such as signal processing, multimedia codecs, and matrix math^[22].

Page Fault

A page fault is an architectural exception triggered by the Memory Management Unit (MMU) when an instruction references a virtual address whose page is not currently present in physical RAM^[23][24]. The hardware suspends the executing program and transfers control to the operating system's page fault handler^[23]. The operating system retrieves the missing page from disk storage, writes it into main memory, updates the page table, and resumes execution at the faulting instruction^[23][25].

Translation Lookaside Buffer (TLB)

The TLB is a dedicated hardware cache integrated into the MMU that stores the most recently used page table entries^[23][25]. Because page tables reside in main RAM, an unbuffered virtual memory reference would require two physical memory accesses for every single operation^[25]. A TLB hit allows the processor to translate a virtual address into a physical address immediately without reading memory-resident page tables^[25].

Virtually Indexed Physically Tagged (VIPT) Cache

A VIPT cache uses the index bits of the CPU's virtual address to look up the cache set, while the MMU translates the virtual page number into a physical address in parallel^[26]. Once the cache set lines are accessed, the cache compares stored physical tags against the translated physical address tag from the MMU^[26]. This design provides the speed of virtual indexing while eliminating the need to flush the cache on operating system context switches^[26].

Polling (Programmed I/O)

Polling is an I/O communication method where the CPU executes a loop to repeatedly read the status register of an I/O interface until the peripheral signals readiness^[27]. Because peripheral devices operate significantly slower than processors, the CPU wastes numerous clock cycles executing idle check instructions^[27]. Furthermore, moving data requires the processor to fetch individual transfer instructions and route each byte through internal CPU registers^[27].

Direct Memory Access (DMA)

Direct Memory Access is a hardware transfer mechanism where a dedicated DMA controller transfers data blocks directly between an I/O peripheral and main RAM^[27][28]. The CPU initiates the transfer by programming the transfer direction, memory addresses, and block size, then relinquishes control of the system bus to the DMA controller^[28]. While the DMA controller drives the bus, the CPU can continue executing instructions undisturbed out of its internal cache until an interrupt signals completion^[28].