Verilog and VHDL Digital Logic Design: Primitives, Descriptions, and Constructs

The first port in the port list of a Verilog gate level primitive is

The one and only output

The Verilog HDL is case sensitive

True

Which HDL description or model is a one to one match with the schematic diagram of a logic circuit?

Structural

The binary/logic operators in Verilog use what kind of characters?

special characters

The Verilog HDL has gate level primitives defined in the language standard and recognized by the compiler/synthesizer

True

Does behavioral description give any hints about how the circuit should be implemented?

No

The statements in an always block are executed

whenever one or more signals in the sensitivity list change

The statements in a procedural block (always/initial in Verilog) are executed

sequentially

We can use functional description inside a procedural block

True

We can instantiate modules inside a procedural block

False

A test bench can be synthesized

False

A test bench has no input and output ports

True

Exhaustive verification applies to

all possible input combinations

The initial Verilog procedural block is executed

Only once

The signals assigned a value inside a procedural block (always or initial in Verilog) have to be declared of type

reg

A VHDL component is comprised of

one entity and one or more architectures

VHDL does NOT have built-in gate level primitives

True

High-impedance or tri-stated outputs are used to transfer data

from multiple sources to one destination

A VHDL entity contains the component interface information

True

VHDL logic operators use

letter names such as AND OR XOR etc

Behavioral description uses

procedural statements

The sensitivity list should contain all signals used inside the process on the right hand side of assignments

True

The statements in a VHDL process are executed

sequentially

All project files that contain descriptions belong automatically to the work library

True

If-else and/or case statements can be nested

True

In Verilog the size of an instance using a parameterized module can be chosen

by providing a new value for the parameters at the time of instantiation

In named (or explicit) association (or port mapping) the order of associations

does NOT matter

Multi-bit signals in Verilog are described as

vectors

In an ECA the carry-outs ripple (propagate) from the least significant bit position to the most significant bit position

True

To create parameterized descriptions using module instances

we need to use the generate for loop or construct

In VHDL a generic component can be resized from the default values at instantiation time by

providing another value for the generics

In a RCA the cout is known after all carries have propagated from

the LSb to the MSb position

Multi-bit signals in VHDL are described as

vectors

To create generic descriptions using component instances

we can use the VHDL for generate loop in the concurrent block of code

In VHDL generic mapping maps

generics to positive integer values

At instantiation time the value of a parameter in Verilog can be specified

in more than one way

The generate for loop in Verilog allows the description of a circuit with arbitrary structure

False

The for generate loop in VHDL allows the description of a circuit with repetitive periodic structure

True

The Verilog generate for loop can only be used in a concurrent block of code

True

The VHDL for generate loop can only be used in a procedural block of code

False

A NOT gate can be implemented using a 2-to-1 mux by

connecting the NOT input to the select input and tying data input 0 to 1 and data input 1 to 0

In an FPGA LUT the data inputs of the multiplexer are driven by

values stored in storage elements

If we expand a function by 2 variables we need at least a

4 to 1 mux

What are the steps to the application of Shannon's expansion theorem?

expansion rearrangement of function simplification of co-factors

The canonical form of a function is

the SOP of all terms for which the function is 1

If we add two numbers of the same sign and the sign of the result is the opposite sign did overflow occur?

Yes

The zero status bit is 1 if the result is

0

For two's complement represented numbers the negative status bit is 1 if the MSbit of the result is

1

Shift right arithmetic replicates the MSbit to

maintain the sign of the operand in two's complement

A rotate left through carry allows us to transfer into the carry the value of the blank of the operand

MSbit

What is the first port in the port list of a Verilog gate level primitive?

The one and only output

Is the Verilog HDL case sensitive?

True

Which HDL description or model matches one to one with the schematic diagram of a logic circuit?

Structural

What kind of characters do binary/logic operators in Verilog use?

Special characters

Does the Verilog HDL have gate level primitives defined in the language standard?

True

Does behavioral description give hints about how the circuit should be implemented?

No

When are the statements in an always block executed?

Whenever one or more signals in the sensitivity list change

How are the statements in a procedural block executed?

Sequentially

Can we use functional description inside a procedural block?

True

Can we instantiate modules inside a procedural block?

False

Can a test bench be synthesized?

False

Does a test bench have input and output ports?

False

What does exhaustive verification apply to?

All possible input combinations

How many times is the initial Verilog procedural block executed?

Only once

What type must signals assigned a value inside a procedural block be declared as?

reg

What comprises a VHDL component?

One entity and one or more architectures

Does VHDL have built-in gate level primitives?

False

What are high-impedance or tri-stated outputs used for?

To transfer data from multiple sources to one destination

What information does a VHDL entity contain?

The component interface information

What do VHDL logic operators use?

Letter names, such as AND, OR, XOR, etc.

What does behavioral description use?

Procedural statements

What should the sensitivity list contain?

All signals used inside the process on the right hand side of assignments

How are the statements in a VHDL process executed?

Sequentially

Do all project files that contain descriptions belong automatically to the work library?

True

Can if-else and/or case statements be nested?

True

How can the size of an instance using a parameterized module be chosen in Verilog?

By providing a new value for the parameters at the time of instantiation

In named (or explicit) association, does the order of associations matter?

No

How are multi-bit signals in Verilog described?

Vectors

In an ECA, how do carry-outs ripple?

From the least significant bit (LSb) position to the most significant bit position (MSb)

What do we need to create parameterized descriptions using module instances?

The GENERATE FOR loop/construct

How can a generic component in VHDL be resized at instantiation time?

By providing another value for the generics

When is the cout known in a RCA?

After all carries have propagated from the LSb to the MSb position

How are multi-bit signals in VHDL described?

Vectors

What do we use to create generic descriptions using component instances in VHDL?

The VHDL FOR GENERATE loop in the concurrent block of code

What does VHDL generic mapping do?

Maps generics to positive integer values

How can the value of a parameter in Verilog be specified at instantiation time?

In more than one way

Can the generate For loop in Verilog describe a circuit with arbitrary structure?

False

What does the FOR GENERATE loop in VHDL allow?

The description of a circuit with repetitive (periodic) structure

Can the Verilog GENERATE FOR loop only be used in a concurrent block of code?

True

Can the VHDL FOR GENERATE loop only be used in a procedural block of code?

False

How can a NOT gate be implemented using a 2-to-1 mux?

Connecting the NOT input to the select input of the mux, and its data input 0 connected to 1 and 1 connected to 0 respectively

In a FPGA LUT, what drives the data inputs of the multiplexer?

Values stored in storage elements

What do we need to expand a function by 2 variables?

At least a 4 to 1 mux

What are the steps to apply Shannon's expansion theorem?

Expansion, re-arrangement of function, simplification of co-factors

What is the canonical form of a function?

The sum of products (sop) of all terms for which the function is 1

If we add two numbers of the same sign and the sign of the result is of the opposite sign, did overflow occur?

Yes

When is the zero (Z) status bit 1?

If the result is 0

For 2sC represented numbers, when is the negative status bit (N) 1?

If the MSbit of the result is 1

What does shift right arithmetic replicate?

The MSbit to maintain the sign of the operand in 2sC

What does a rotate left through carry (RLC) allow us to transfer into the carry?

The value of the MSbit of the operand