Moderni tietokone v2

Temporal Locality

Temporal locality is the principle that if the CPU accesses a memory location once, it is very likely to access that exact same location again in the near future. The memory system exploits this behavior by keeping recently accessed data and instructions inside small, fast SRAM cache memory close to the CPU core so it does not have to retrieve them from slow main RAM. This happens frequently in loops when updating counter variables or when calling the same subroutines repeatedly.

Spatial Locality

Spatial locality is the principle that if the CPU accesses one specific memory address, it is very likely to access nearby memory addresses soon after. To take advantage of this behavior, hardware caches do not fetch just a single byte on a cache miss; instead, they copy an entire contiguous block called a cache line from main memory into the cache. This ensures that programs running sequential instructions or stepping through array elements get immediate cache hits on subsequent reads.

Cache Hit vs. Cache Miss

A cache hit occurs when the CPU requests data and finds it immediately inside the high-speed cache, delivering the value in just one or two clock cycles without using the shared system bus. In contrast, a cache miss happens when the requested address is not present, forcing the processor to pause and fetch an entire data block from main RAM. This waiting period is called the miss penalty, and it creates idle stall cycles where the CPU pipeline cannot make progress.

Write-Through vs. Write-Back

Write-through and write-back are two different cache update policies used when the CPU writes data to memory. Under write-through, the CPU writes data to both the cache and main memory at the same time, which keeps memory safe and consistent but slows down execution because every write must wait for slow RAM. Under write-back, the CPU writes data exclusively into the cache and marks the block with a dirty bit, updating main memory only when that modified block is evicted to make room for new data, which is much faster and saves system bus bandwidth.

The Three Miss Categories (The 3 Cs)

Cache misses are categorized into three fundamental classes known as compulsory, capacity, and conflict misses. Compulsory misses, also called cold misses, happen the very first time a program accesses a block of data because that block has never been loaded before. Capacity misses occur when the cache is simply too small to hold all the active data that the working program requires, while conflict misses happen in direct-mapped or set-associative caches when multiple active memory blocks happen to map to the exact same cache set and repeatedly overwrite one another.

Control Hazard (Branch Hazard)

A control hazard occurs in a pipelined processor when a branch instruction alters the program counter and the CPU does not know which instruction to fetch next. Because branch conditions and target addresses are evaluated in later pipeline stages, the fetch stage would have to wait several clock cycles unless the processor guesses the outcome. Hardware mitigates this penalty by using techniques like branch prediction, branch target buffers, and branch delay slots to keep fetching instructions without stalling the pipeline.

Structural Hazard & Pipeline Bubble

A structural hazard is a hardware resource conflict where two or more overlapping instructions in the pipeline need to use the exact same physical hardware component during the same clock cycle. When this happens, the hazard detection unit must insert an idle clock cycle called a pipeline bubble, which acts like an empty operation that moves through the pipeline while one instruction waits. Designers eliminate structural hazards by adding duplicate hardware resources, such as creating separate L1 instruction and data caches instead of sharing a single memory port.

Data Hazard & Forwarding (Bypassing)

A data hazard arises when an instruction needs the result of a previous instruction that has not finished writing its value back to the register file yet. Hardware forwarding, or bypassing, solves this by using special internal routing wires to send the calculated output directly from the ALU or memory stage straight into the input of the next dependent instruction without waiting for the register write-back. However, if an instruction immediately uses the result of a memory load instruction, forwarding alone cannot prevent a delay, so the hardware must insert a one-cycle load-use stall.

Branch Target Buffer (BTB)

A Branch Target Buffer is a small, specialized cache on the CPU chip that stores the target memory addresses of previously executed branch instructions along with prediction information. During the instruction fetch stage, the processor checks the BTB using the current program counter before the instruction is even decoded. If a match is found and the branch is predicted as taken, the processor immediately redirects instruction fetch to the stored target address on the very next clock cycle, completely avoiding pipeline stalls.

Dynamic Branch Prediction

Dynamic branch prediction is a hardware technique that tracks and learns the behavior of conditional branches at runtime to accurately guess whether they will be taken or not taken. It utilizes a Branch History Table containing 1-bit or 2-bit saturating counters that update their state every time a branch executes. Using 2-bit counters provides the significant advantage that a loop branch exiting once will not immediately change the prediction, preventing expensive pipeline flush penalties on deeply pipelined processors.

Interrupt Latency

Interrupt latency is the total amount of time that elapses between when a hardware peripheral asserts an interrupt request signal and when the CPU executes the first instruction of the interrupt service routine. This delay exists because the processor must finish its current atomic instruction and save its active working registers to the stack before switching tasks. Minimizing interrupt latency is essential in real-time embedded systems where the computer must react predictably to time-critical physical events.

Hardware Exception Stacking

Hardware exception stacking is an ARM Cortex-M feature where the processor automatically pushes eight core registers—r0 through r3, r12, the Link Register, the Program Counter, and the Status Register—onto the active stack when an interrupt arrives. Because this context saving is performed entirely by dedicated hardware circuits rather than software instructions, standard C functions can serve directly as interrupt service routines without requiring special compiler wrappers. Once stacking completes, the processor branches directly to the handler address specified in the interrupt vector table.

EXC_RETURN

When an interrupt occurs on an ARM Cortex-M processor, the hardware automatically loads a special reserved bit pattern called EXC_RETURN into the Link Register. When the interrupt service routine finishes and executes a standard return branch instruction, the CPU detects this unique code instead of a regular memory address while operating in privileged Handler Mode. Seeing this code triggers the hardware exception exit sequence, causing the processor to automatically pop the eight saved registers from the stack and resume the interrupted application cleanly.

Tail Chaining

Tail chaining is an ARM Cortex-M hardware optimization that activates when an interrupt handler finishes and another pending interrupt is waiting to be serviced. Instead of restoring all the saved registers from the stack only to immediately push them right back for the second interrupt, the processor skips both the unstacking and restacking steps and branches straight into the next interrupt handler. This reuses the valid context already saved on the stack, drastically reducing the latency between consecutive interrupts.

Late Arrival

Late arrival is an interrupt optimization in ARM processors that occurs when a higher-priority interrupt arrives while the hardware is already in the middle of stacking registers for an earlier, lower-priority interrupt. Rather than aborting the stacking process or waiting for the low-priority handler to complete, the processor simply finishes saving the registers and immediately branches to the higher-priority routine first. This ensures that the time-sensitive high-priority task runs without delay while avoiding any redundant context-saving cycles.

Main Stack Pointer (MSP) vs. Process Stack Pointer (PSP)

The ARM Cortex-M architecture provides two physically separate stack pointers that share the same register name, r13, to keep system memory secure. The Main Stack Pointer is used by the operating system kernel and all interrupt service routines, while the Process Stack Pointer is assigned to regular user application threads. This division ensures that even if a user program crashes or overflows its own stack, the critical operating system kernel and interrupt stacks remain protected from memory corruption.

Cache Coherency & Bus Snooping

Cache coherency is a critical challenge in symmetric multiprocessing systems where multiple CPU cores have private caches but share one common main memory across a system bus. If one core modifies a piece of data in its private cache, other cores could easily read outdated, stale values from their own local caches unless the system coordinates updates. To prevent this, each cache controller implements bus snooping, continuously monitoring all traffic broadcast across the shared bus so it can immediately invalidate or update its local copy whenever another core writes to that address.

MESI Protocol

The MESI protocol is a widely used hardware bus-snooping protocol that enforces cache coherency across multiple processor cores by assigning one of four states to each cache line. A line is marked Modified if it has been updated in that cache and differs from main RAM, Exclusive if it is clean and present only in that single cache, Shared if it is clean and shared across multiple caches, or Invalid if its data is outdated and unusable. When a core wants to write to a line marked Shared, it broadcasts an invalidation signal over the bus so all other caches set their copies to Invalid.

Arithmetic Logic Unit (ALU) & Datapath

The Arithmetic Logic Unit is the primary calculation circuit inside the CPU datapath that carries out basic integer arithmetic such as addition and subtraction, as well as bitwise logical operations like AND, OR, and shifts. The datapath itself consists of all the physical interconnected hardware units—including the ALU, register files, multiplexers, and internal buses—that route and transform data during execution. The control unit coordinates this entire system by decoding incoming machine instructions and sending control signals to direct how the datapath processes the operands.

SIMD (Single Instruction, Multiple Data)

SIMD is an architectural execution model from Flynn’s Taxonomy where a single instruction broadcast by the control unit performs the exact same operation simultaneously across multiple data values packed into wide registers. Modern processors implement this using dedicated vector execution units such as Intel AVX or ARM NEON, which can process arrays of numbers in parallel during a single clock cycle. This architectural design provides massive performance speedups for data-intensive applications like video encoding, 3D graphics, audio processing, and machine learning computations.

Page Fault

A page fault is an operating system exception that occurs when the CPU attempts to access a virtual memory address whose corresponding memory page is not currently present in physical RAM. When this happens, the Memory Management Unit halts the executing program and transfers control to the operating system's page fault handler. The operating system allocates an empty page frame in RAM, reads the missing page data from secondary storage like an SSD, updates the page table mapping, and then restarts the interrupted instruction so execution can continue normally.

Translation Lookaside Buffer (TLB)

The Translation Lookaside Buffer is a small, high-speed hardware cache built into the Memory Management Unit that stores recently used virtual-to-physical address translations from the page table. Because page tables reside in main memory, an unbuffered virtual memory system would require two slow memory accesses for every single instruction: one to translate the address and another to access the actual data. A TLB hit enables the hardware to translate a virtual address into a physical address in a single clock cycle, completely avoiding extra page table lookups in RAM.

Virtually Indexed Physically Tagged (VIPT) Cache

A Virtually Indexed Physically Tagged cache uses index bits taken directly from the CPU's virtual address to look up the cache set, while the Memory Management Unit translates the virtual page number into a physical address in parallel at the exact same time. Once the set is located and the physical address is ready, the cache compares the physical tags stored in the cache lines with the physical tag produced by the MMU to determine if there is a hit or miss. This approach combines the high speed of virtual indexing with the safety of physical tagging, avoiding complex virtual aliasing errors and removing the need to flush the cache during process context switches.

Polling (Programmed I/O)

Polling, or programmed I/O, is a communication method where the CPU repeatedly executes a software loop that reads the status register of an I/O device to check whether it is ready to transfer data. Because physical peripheral devices operate much more slowly than processors, polling forces the CPU to waste billions of clock cycles in busy-wait loops checking mostly idle hardware. It also requires the processor to move every single byte through its internal registers, making it inefficient for general-purpose computers, although it remains useful in simple microcontrollers or for extremely fast hardware.

Direct Memory Access (DMA)

Direct Memory Access is a hardware transfer mechanism where a specialized DMA controller moves large blocks of data directly between an I/O peripheral and main memory across the system bus without routing each byte through the CPU. The processor simply configures the transfer parameters—such as the memory start address, transfer direction, and number of bytes—and then yields control of the bus so it can continue executing other software tasks out of its cache. Once the entire data block has been transferred, the DMA controller sends a single hardware interrupt to notify the CPU that the transfer is complete.