Digital Design 2 Midterm

A 4-bit shift register is composed of ___ flip-flops internally.

4

Select the primary functions of a shift register.

data storage, data movement

For a 4-bit Serial in-Serial out shift register, it takes ___clock cycle(s) to fill, and ___clock cycle(s) to SHIFT out all data.

4, 4

For a 4-bit Serial in-Parallel out shift register, it takes ___clock cycle(s) to fill, and ___clock cycle(s) to SHIFT out all data.

4, 1

For a 4-bit Parallel in-Serial out shift register, it takes ___clock cycle(s) to fill, and ___clock cycle(s) to SHIFT out all data.

1, 4

For a 4-bit Parallel in-Parallel out shift register, it takes ___clock cycle(s) to fill, and ___clock cycle(s) to SHIFT out all data.

1, 1

A bidirectional shift register can transfer data both right and left through its internal flip-flops.

True

In a Johnson counter, the _________ of the last flip flop is connected to the input of the first flip flop

complement of the output

In a ring counter, the _________ of the last flip flop is connected to the input of the first flip flop

output

Select all the applications that a shift register can be used for.

time delay, serial-to-parallel data converter, UART (universal asynchronous receiver transmitter)

A UART is composed of both a serial-to-parallel data converter and a parallel-to-serial data converter.

True

The number of bits in a shift register is equal to the number of ___________________.

internal flip-flops

A ring counter has the advantage over a Johnson counter that it doesn't require ____________.

decoding gates

A state machine can have an infinite number of states.

False

The number of states in a state machine is called the _____________.

modulus

A Moore machine does not rely on external input to drive output.

True

A Mealy machine can have a variable (but still finite) number of states, because outputs can be affected by inputs.

True

_________________ is an example of a Moore state machine.

A Johnson counter

_________________ is an example of a Mealy state machine.

A synchronous counter

In an asynchronous counter, _________________________.

the internal flip-flops do not share a common clock.

In a synchronous counter, _________________________.

every internal flip-flop uses the same clock signal.

An asynchronous counter is also referred to as a __________________ because of the propagation delay between internal flip-flops.

ripple counter

The maximum modulus for a counter with 4 flip-flops is ______.

16

To reset a counter before hitting the maximum state, you must use ___________________.

partial decoding

A ______________ in a decade counter is when the output goes to an invalid state for a short time before the counter resets.

glitch

In a synchronous counter, __________________ are typically used because the additional states eliminate the need for additional logic

J-K flip flops

An Up/Down synchronous counter can count both directions through its finite states, and can also skip over states.

False

For any counter that uses J-K flip-flops, the transition table used when designing will be identical.

True

When counters are cascaded, the last-stage output of the first counter is connected to the input of the next counter.

True

To get the total modulus of cascaded counters, ________________________________.

multiply the individual moduli together.

Synchronous cascading is more complex than asynchronous cascading, because each counter needs a terminal count to enable it at the right time.

True

Instead of starting at 0, a cascaded counter can truncate its sequence by

presetting the initial state

To prevent a glitch in a truncated counter, strobing _____________________________________.

only enables the decoded output after glitches have had time to disappear

A PAL is _______________________.

one-time programmable

A GAL is _______________________.

reprogrammable

Both a PAL and a GAL consist of __________________ AND gates and _______________ OR gates.

programmable, fixed

Both PALs and GALs create ___________________ expressions.

SOP

A PAL uses __________ to connect input lines to its internal gates.

fuses

A GAL uses __________ to connect input lines to its internal gates.

EEPROM

In simplified notation for a PAL/GAL diagram, multiple lines into gates are symbolized by __________________.

a single line

In simplified notation for a PAL/GAL diagram, the exact number of lines into gates are symbolized by __________________.

a number and a slash

In simplified notation for a PAL/GAL diagram, programmable links that are in use are symbolized by __________________.

an ‘x’

A macrocell configured in registered mode uses a __________________.

flip-flop

PALs and GALs are examples of ________.

SPLDs

A CPLD (Complex Programmable Logic Device) is composed of multiple _________.

SPLDs

In classic CPLD architecture, the PIA is built as _______________

a channel

In LUT CPLD architecture, the PIA is built as _______________

rows and columns

A shared expander uses _____________ to increase the number of product terms in another macrocell.

negated individual variables through an inverter gate

A parallel expander uses _____________ to increase the number of product terms in another macrocell.

unused product terms in an SOP expression

A PLA differs from a PAL because it has ___________________.

reprogrammable OR gates

Logic modules in an FPGA contain ______________ with associated logic.

a lookup table

A logic module programmed for normal mode usually generates __________________.

combinational logic

Select all things needed to program a programmable logic device.

Programming hardware (cable or board), Computer, Programmable Device, Software

Which of the following is NOT a required input or output for a Test Access Port (TAP)

Test Reset (TRST)

Boundary scan testing is limited to testing one device at a time.

False