Introduction to Embedded Systems

Practice vocabulary flashcards covering the core concepts, performance metrics, hardware components, and design methodologies of embedded systems.

Embedded System (ES)

A hardware/software computing system designed for a specific purpose or dedicated application, distinguishing it from general-purpose computing platforms such as PCs, mainframes, and servers.

Reactive System

A system characteristic where the computing device interacts continuously with its surrounding physical environment via sensors and actuators rather than merely executing batched computations.

Real-Time System

A computing system where operations must strictly meet real-time deadlines, meaning the functional correctness depends not only on the logical output but also on when that output is delivered.

On-Chip Peripherals

Specialized hardware modules integrated onto an MCU or SoC (such as GPIO, ADC, Timer, I2C, SPI, UART, and USB) that serve as interfaces bridging the CPU and memory to external sensors and actuators.

Electronic Control Unit (ECU)

An embedded computing module in automotive systems dedicated to controlling a specific vehicle subsystem; modern vehicles feature dozens to over $100$ ECUs, which are increasingly consolidated into domain and zonal computers.

Anti-Lock Brake System (ABS)

An automotive embedded safety system that actively modulates hydraulic brake pressure during deceleration to prevent wheel lockup and preserve vehicle steering control.

Design Metric

A measurable attribute of a system's implementation (such as unit cost, NRE cost, size, execution speed, power consumption, or time-to-market) against which conflicting design constraints are optimized.

Unit Cost

The recurring monetary expense associated with manufacturing each individual copy of an embedded system, excluding non-recurring engineering expenses.

NRE (Non-Recurring Engineering) Cost

The one-time monetary expenditure incurred to research, design, develop, and verify a product before high-volume commercial production begins.

Market Window

The defined period during which a commercial product achieves its peak sales demand before market interest declines; falling outside this window leads to severe revenue losses.

Percentage Revenue Loss (Market Entry)

A metric quantifying the cost of market delay modeled by a triangular sales trajectory, represented mathematically as $L = \frac{D(3W - D)}{2W^2} \times 100\%$, where $2W$ is product lifetime and $D$ is the delay duration.

Latency

The execution or response duration required to complete a single discrete task from initiation to completion, such as an edge camera detecting an object in $25\,\text{msec}$.

Throughput

The total volume of work or number of discrete tasks an embedded system completes per unit of time, such as processing $50\,\text{frames per second}$.

General-Purpose Processor (CPU)

A programmable computing device (such as the ARM Cortex-M4) equipped with program memory, a broad datapath, a large register file, and a general ALU designed to offer high flexibility and low NRE cost across varied workloads.

Fixed-Function Hardware

A custom digital accelerator circuit or coprocessor (such as a JPEG codec) designed to execute exactly one fixed program or operation with minimal flexibility, maximizing execution speed and energy efficiency.

Application-Specific Instruction-Set Processor (ASIP)

A domain-specific programmable processor (such as a DSP with a hardware multiply-accumulate unit) optimized for a specialized class of algorithms, providing a balance between CPU flexibility and hardware efficiency.

IC Process Technology (Node)

A designated generation of semiconductor manufacturing technology (such as $130\,\text{nm}$, $28\,\text{nm}$, $7\,\text{nm}$, or $3\,\text{nm}$) that historically referenced transistor dimensions but now represents technology milestones and packing density.

Full-Custom IC Design

An integrated circuit design methodology where all layers and transistors are custom-placed, sized, and routed manually down to the silicon level, yielding maximum PPA optimization at the cost of extreme NRE expense.

Standard-Cell ASIC

An application-specific integrated circuit synthesized using automated EDA tools from a pre-designed library of logic gates, flip-flops, and memory blocks, offering a balance of high performance and reasonable design productivity.

Field-Programmable Gate Array (FPGA)

A prefabricated integrated circuit containing programmable logic blocks, interconnects, memories, and DSP blocks that can be configured and reconfigured after fabrication, offering low NRE cost and rapid prototyping.

Moore's Law

An empirical semiconductor industry trend recognized by Intel co-founder Gordon Moore stating that the number of transistors packed onto leading-edge integrated circuits roughly doubles every two years.

Hardware/Software Partitioning

The system-level design phase where system requirements and architectural tasks are divided into those that will execute as software on processors versus those implemented in dedicated hardware circuits.

Logic Synthesis

An automated Electronic Design Automation (EDA) process that compiles Register-Transfer Level (RTL) hardware descriptions into an optimized, gate-level netlist of library cells.

High-Level Synthesis (HLS)

An electronic design automation toolflow that automatically converts algorithmic specifications written in high-level programming languages (such as C, C++, or SystemC) directly into RTL hardware implementations.

Physical Design

The downstream IC design stage that takes a synthesized gate-level netlist and carries out placement, clock-tree synthesis, and routing to establish the physical geometric layout of the chip.

IP (Intellectual Property) Block

A pre-designed, pre-verified functional hardware block (such as an ARM CPU core, memory controller, USB controller, or NPU) licensed or reused to accelerate SoC design and reduce design risk.

Formal Verification

A verification technique that relies on rigorous mathematical proofs to prove whether an implementation guarantees specific architectural properties across all operational inputs, catching difficult corner cases missed by simulation.

The Mythical Man-Month

A software engineering and management axiom demonstrating that adding personnel to a late development project often delays it further due to the non-linear growth of communication and coordination overhead.