Computer Organization Exam 3 Flashcards

Memory Volatility

Refers to the characteristic of computer memory that determines whether data is retained when power is lost. Volatile memory requires power to maintain the stored information, with the contents disappearing when power is removed but is the least expensive. Non-volatile memory retains data without power, providing long-term storage but has slower access times. The Hard Drive is not a non-volatile memory.

Memory Access Paradigm

Random access is an access pattern where any arbitrary storage location can be read or written directly in constant time. Sequential access is an access pattern where data must be accessed in a fixed, ordered stream, where it’s often implemented as FIFO.

ROM (Read-Only Memory)

A permanent memory whose values are fixed during manufacturing and can be read but never overwritten or changed.

PROM (Programmable Read-Only Memory)

A type of ROM that can be written after manufacture, but altering it is time-consuming and historically required UV light exposure.

EEPROM

An electricallly erasable and reprogrammable non-volatile memory (PROM) that can be modified while remaining installed in a circuit.

Memory Hierarchy

Primary And Secondary Memory

Primary memory is high-speed, volatile, expensive, and solid-state memory. Secondary memory is low-speed, non-volatile, cheaper, and electromechanical memory.

Von Neumann Architecture

A unified physical memory space that stores both program instruction and program data. Instruction and data bits look identical, but a bit can be interpreted as instructions only when pointed to and fetched by the program counter (PC).

Fetch-Store Paradigm

The fundamental memory interface consisting soley of fetching (reading) from an address and storing (writing) to an address.

Random Access Memory (RAM)

The main physical memory of a computer system. Allows direct, random access to any storage location with consistent access times, as opposed to sequential (FIFO) access. Typically volatile, meaning its stored contents are lost when power is removed.

Static RAM (SRAM)

Uses bistable latch circuits/flip-flops made of logic gates to hold each bit without periodic recharging. The advantages are high speed and no extra refresh circuitry required while the disadvantages are power consumption, heat, and high cost.

Dynamic RAM (DRAM)

Acts like a capacitor where each bit is stored as an electrical charge. Given any electronic storage device gradually loses charge, when left for a long time, a bit changes from logical 1 to logical 0. Repeatedly steps through each location and reads its value, and writes the values back into the same location.

Memory Density

Measures memory cells per square area of silicon. Usually stated as number of bits on standard size chip. A higher density chip generates more heat.

Memory Latency

The elapsed time between the start of an individual memory access request and the delivary of the completion response. In many memory technologies, the times required to fetch informatio from meory differs from the time required to store information in memory.

Memory Controller

A hardware unit that connects the processor to physical memory via control signals. Its functions are to translate CPU requests into hardware signals, abstracts chip organization, manages DRAM refresh cycles, and routes address, data, and control lines.

Cold Boot Attack

A physical attack that exploits DRAM data remanence after power loss to extract sensitive memory contents such as cryptographic keys. The capcitor charge decays in seconds at room temperature and only gives seconds of usable data after power loss. At -50 degrees celcius it gives minutes of usable data and in liquid nitrogen it gives hours, which is the key to extracting the memory contents.

Synchronous Memory

Memory coordinates directly with the CPU system clock to eliminate timing delays and enable predictable access windows in both the memory and processor. Uses the processor’s clock to eliminate timing delays and establish precise, predictable access windows for read and write operations. The processor knows precisely when data will arrive and can schedule other pipeline tasks during memory operations.

Memory Cycle Time

Time that must elapse between two successive memory operations, with it being a more accurate measure than latency. The read cycle time (tRC) and write cycle time (tWC) are the minimum time required between consecutive read or write operations, including latency and the required DRAM refresh/reset time.

Memory Data Rate Memory

Technologies that transfer multiple data words per clock cycle, which avoids a memory bottleneck and improves memory performance with hardware running at a multiple of CPU clock.

System Bus

A parallel set of communication wires connecting the CPU, memory, and I/O devices, divided into the control bus, address bus, and data bus. The amount of memory that can be transferred to the computer simultaneously is determined by the bus between the computer and controller.

Memory Transfer Size

The number of data bits (e.g., 16, 32, or 64 bits) that can be read from or written to physical memory across the bus in a single operation.

Word Size

Bits of physical memory are divided into blocks of N bits each, with a group of N bits being called a word. N is known as the width of a word or the word size, with a computer often characterized by its word size (i.e. 64-bit computer). A larger word size boosts processing throughput by transferring more data per cycle, but demands more parallel wires, increases chip cost, and consumes more power.

Physical Memory Addressing

An addressing architecture where each word of memory is assigned a unique number known as a physical memory address. The underlying hardware views physical memory as an array of words, where a word is equal to the memory transfer size. The underlying memory controller always transfers a complete word on every read or write request, even if the CPU only requires a fraction of that word.

Byte Addressing

An addressing scheme presented to the processor and programmer where every single 8-bit byte in memory is assigned its own unique address. Underlying memory can still use word addressing. Performed by a memory controller, which allows the processor to use byte addressing and allows physical memory to use word addressing.

Address Translation

Used to find byte in word addressing. For arithmetic, word address is given by: W = B/N, and is given by: B mod N.

Example:

• N = 4

• Byte address: 11

• Found in word 2 at offset 3

For bit extraction, because hardware architects select N as a power of 2 (N = 2^k), the division and modulo operations are implemented without arithmetic logic. The higher-order bits of the byte address form the word address (via bit-shifting), and the lowest k bits form the byte offset.

Byte Alignment

Refers to the integer storage in memory, placing multi-byte data types (like 32-bit or 64-bit integers) at memory addresses that are integer multiples of their size or the physical word boundary. Some architecture requires integers in memory to correspond to word in underlying physical memory while other architectures allows integers to be unaligned, but fetch and store operations operate much slower.

Unaligned Memory Access

If an integer spans across two adjacent physical words, the processor must execute two separate memory read cycles, perform bit-shifting to reassemble the data, and execute two write-back cycles if modifying the value, significantly reducing performance.

Address Space

The maximum range of unique memory locations that a processor can reference, strictly limited by the width of its address bus or pointer size (2^{address bits}).

Example: 32-bit address can represent 2³² = 4,294,967,296 unique addresses (~4GB).

Memory Dump

A diagnostic capture and printable hex/ASCII representation of the raw binary contents stored across memory addresses at a specific instant. Every line of output specifies memory address and bytes starting at that address. Primarily used by programmers for debugging.

Memory Banks

A hardware design where physical memory is divided into multiple independent modules, each managed by its own controller to allow concurrent memory operations.

Transparent Banks: The hardware and memory controller handle bank selection automatically without the programmer needing to know the underlying bank layout.

Opaque Banks: The physical bank organization is exposed directly to software, requiring the programmer/compiler to strategically place simultaneous data accesses in separate banks to prevent contention.

Memory Interleaving

A hardware technique related to memory banks that spreads consecutive memory addresses across N distinct physical memory modules. The low-order bits of the memory address determines which physical module holds the data, enabling the system to stream sequential memory requests in parallel without waiting for a single module's recovery/cycle time. This is also known as N-way interleaving, where N is number of physical memories.

Content Addressable Memory (CAM)

A specialized hardware memory that searches by data content rather than memory address (often termed associative memory). Instead of supplying an address to retrieve data, the CPU supplies a search query/key, and the CAM queries all rows (slots) in parallel to return the corresponding memory address/slot where that value resides in a single clock cycle. The memory could be thought of as a two-dimensional array.

Virtual Memory

An architectual mechanism that abstracts and hides the physical memory details, presenting each program with an isolated, convenient logical memory space and virtual address space. Provides a view of memory that is more convenient to a programmer, gives a homogeneous integration of hardware and can overcome limitations of physical memory and physical addressing.

Job 1 (Combine): Integrates disparate physical storage (multiple DRAM modules and secondary disk storage) into one seamless, uniform address space that appears larger than actual physical memory. “Virtual” = looks like it’s there, but it isn’t

Job 2 (Divide): Partitions a single shared physical memory into multiple private address spaces. Each running process gets the illusion that it owns the machine from address 0 upward, preventing processes from reading or corrupting each other's data. “Virtual” = everyone gets their own illusion

Memory Management Unit (MMU)

A dedicated hardware unit embedded inside modern processor cores responsible for high-speed address translation between virtual memory addresses and physical memory addresses. Intercepts every instruction fetch and data access from the CPU, maps the requested virtual address to the underlying physical frame using configured lookup structures (page tables/TLB), and triggers hardware faults (e.g., page faults) if a page is unmapped or protected.

Virtual Address

A logical memory address generated by the processor while executing program code. It does not correspond directly to a physical RAM pin/bus location until translated by the MMU.

Virtual Address Space

The complete set of all possible virtual addresses that a program can access (e.g., 2³² addresses for 32-bit, 2⁶⁴ for 64-bit architectures). Each process receives its own distinct virtual address space starting at 0. Can be larger or smaller than physical memory.

Powers Of Two Address Partitioning

Performing arithmetic division or comparison on an MMU chip during every clock cycle is too slow and power-expensive. Instead, when memory chunks are sized as powers of two (2^k), the MMU performs translation instantaneously via bit-masking/shifting:

• The higher-order bits select the memory module, segment, or page.

• The lower-order bits determine the exact byte offset within that target block.

Multiple Physical Memory Mapping

Many computers have more than one physical memory system, with each physical memory having the ability to be optimized for a specific purpose and using a unique technology (e.g., SRAM or DRAM)

Contiguous Address Space: An arrangement where all virtual address blocks map sequentially without gaps to installed physical memory. It is inflexible because all physical memory banks/sockets must be fully populated.

Discontiguous Address Space: An architecture where specific ranges of the address space do not map to physical memory. These unmapped gaps are called holes; attempting to read or write to an address within a hole triggers a system fault/error. Allows the owner to decide how much memory to install.

Base-Bound Registers

Two dedicated hardware registers in the MMU:

• Base Register (B): Specifies the physical starting address of the program's allocated memory block.

• Bound Register (M): Specifies the total allowable size of the virtual address space.

• Physical Address = B + Virtual Address (if Virtual Address< M)

This register is inflexible because programs require large, contiguous blocks of physical RAM. It cannot easily grow allocations dynamically (malloc) or interleave small scattered chunks without causing severe external memory fragmentation.

Memory Segmentation

A fine-grained virtual memory approach that divides a program logically into variable-sized semantic segments (e.g., code, stack, heap, individual procedures). Segments are loaded into physical memory when needed and swapped to disk when idle. When the segment is no longer needed, the OS moves it to the disk.

Demand Paging

The most popular virtual memory technique where virtual and physical memory are chopped into uniform, fixed-size blocks called (typically 4 KB). Virtual memory blocks are called pages while physical memory blocks are called page frames. Pages are only loaded into physical memory frames when actively accessed by the program rather than all at startup. Unused pages remain on secondary disk storage.

Page Table

A per-process one-dimensional array maintained by the operating system in memory that maps virtual page numbers (v) to physical frame numbers (m).

Translation Formula:

• Virtual address is split into: Virtual Page Number (v) and Byte Offset (d)

• For a page size of 2^f bytes (4 KB → f = 12 bits), d = Virtual Address mod 2^f (the lowest f bits)

• The physical frame number m = PageTable[v]

• Physical Address = (m « f) | d. The offset d remains identical between virtual and physical addresses.

Translation Lookaside Buffer (TLB)

A high-speed, on-chip associative cache (built using Content Addressable Memory / parallel comparators) that stores recent (Virtual Page Number → Physical Frame Number) translations. Without it, every single memory access requires at least two physical RAM reads: one to read the page table entry, and a second to access the actual data, making virtual memory unacceptably slow.