Computer Organization: Memory System and Input/Output Organization

Comprehensive vocabulary flashcards covering the Memory System and Input/Output Organization modules based on Computer Organization by Carl Hamacher, Zvonko Vranesic, and Safwat Zaky.

Memory Access Time

The time that elapses between the initiation of an operation and the completion of that operation in a memory system.

Memory Cycle Time

The minimum time delay required between the initiation of two successive memory operations (for example, the time between two successive Read operations).

Word Line

A common line connected to all cells in a row of a memory cell array, driven by the address decoder to activate or select that entire memory word.

Static RAM (SRAM)

A type of volatile memory consisting of circuits (such as flip-flops/latches) capable of retaining their state as long as power is applied, offering access times of a few nanoseconds at a relatively high cost.

SRAM Cell Circuit

A memory cell structure where two transistor inverters are cross-connected to implement a basic flip-flop (latch), connected to bit lines $b$ and $b'$ through access switch transistors $T_1$ and $T_2$ controlled by the word line.

CMOS SRAM Cell

An SRAM cell realization where transistor pairs $(T_3, T_5)$ and $(T_4, T_6)$ form inverters in a cross-coupled latch, providing low power consumption and quick access times.

Dynamic RAM (DRAM)

A type of volatile memory where information is stored as a charge on a capacitor within a cell; because the charge leaks within tens of milliseconds, the contents must be periodically refreshed.

Single-Transistor Dynamic Memory Cell

A compact dynamic memory cell consisting of one transistor $T$ and a storage capacitor $C$, where activating the word line turns on $T$ to connect $C$ to the bit line for read, write, or refresh operations.

Row Address Strobe (RAS) and Column Address Strobe (CAS)

Control signals in a dynamic memory chip with multiplexed addressing: $\overline{\text{RAS}}$ latches the high-order row address bits, and $\overline{\text{CAS}}$ latches the low-order column address bits.

Synchronous DRAM (SDRAM)

A DRAM whose operations and control logic are directly synchronized with an external processor clock signal, allowing rapid bursts of successive data words using an internal column counter.

Memory Latency

The amount of time it takes to transfer a word of data to or from memory.

Memory Bandwidth

The number of bits or bytes of data that can be transferred to or from a memory unit in one second.

Double-Data-Rate SDRAM (DDR SDRAM)

A synchronous DRAM design featuring two cell array banks that transfers data externally on both the rising and falling edges of the clock signal, doubling the effective data transfer rate.

SIMMs and DIMMs

Single In-line Memory Modules and Dual In-line Memory Modules; small printed circuit boards populated with memory chips that plug vertically into motherboard sockets to economize space and facilitate memory expansion.

Memory Controller

A specialized circuit positioned between the processor and DRAM memory that accepts the full address issued simultaneously by the processor, splits it into row and column addresses, and generates $\overline{\text{RAS}}$ and $\overline{\text{CAS}}$ timing signals.

Rambus Memory

A DRAM-based memory architecture using a narrow, high-speed bus with fast differential signaling operating at frequencies such as $400\,\text{MHz}$, using multiple cell array banks to compete directly with DDR SDRAM.

Read-Only Memory (ROM)

A non-volatile memory designed for reading during normal operation, retaining permanent instructions (such as OS boot routines) even when the power supply is cut off.

Programmable Read-Only Memory (PROM)

A ROM variant allowing user programming by selectively burning out internal fuses at point $P$ via high-current pulses to insert logic $1$s into an initially all-$0$ cell array in an irreversible process.

Erasable Programmable Read-Only Memory (EPROM)

A non-volatile memory cell using a floating-gate transistor where data is written by injecting trapped charge and erased entirely by exposing the physically removed chip to ultraviolet (UV) light.

Electrically Erasable Programmable Read-Only Memory (EEPROM)

A non-volatile memory whose contents can be selectively erased and rewritten electrically within the system, although it requires different voltages for erasing, writing, and reading.

Flash Memory

A high-density non-volatile memory technology based on single-transistor trapped-charge cells that allows reading of individual cells but requires entire blocks to be erased before rewriting.

Memory Hierarchy

The multilevel arrangement of storage devices ordered by speed, cost per bit, and capacity: processor registers at the top, followed by L1 cache, L2 cache, main memory (SIMMs/DIMMs), and magnetic disk secondary storage.

Locality of Reference

The programmatic tendency to execute localized instructions repeatedly over periods of time, classified as temporal locality (recently used items are likely to be reused soon) or spatial locality (items with adjacent addresses are likely to be accessed soon).

Cache Hit and Cache Miss

A cache hit occurs when the requested memory word is currently present in the cache; a cache miss occurs when the data is absent, requiring a block transfer from main memory to the cache.

Write-Through Protocol

A cache write policy in which every write operation updates both the cache block and the corresponding main memory location simultaneously.

Write-Back Protocol

A cache write policy (also known as copy-back) where only the cache is updated and marked with a dirty (modified) bit, delaying the update of main memory until that block is replaced.

Load-Through (Early-Restart)

An optimization technique where, upon a read miss, the requested word is immediately forwarded to the processor as soon as it arrives, without waiting for the entire memory block to finish loading into the cache.

Direct Mapping

A cache mapping scheme in which each main memory block maps to a fixed, predetermined cache block according to the formula $j \pmod{128}$, resolving contention simply by replacing the resident block.

Associative Mapping

A cache mapping method in which any main memory block can reside in any block location within the cache, identifying blocks via tag bits that are compared in parallel.

Set-Associative Mapping

A hybrid cache mapping function where cache blocks are grouped into sets, allowing a block from main memory to reside in any block position within its assigned set.

Least Recently Used (LRU) Replacement Algorithm

A cache replacement algorithm used in associative and set-associative caches that identifies and overwrites the block that has gone the longest time without being referenced.

Memory Interleaving

A technique that divides main memory into separate physical modules with individual Address Buffer Registers (ABR) and Data Buffer Registers (DBR), distributing consecutive addresses across consecutive modules to enable parallel memory accesses.

Lockup-Free Cache

A cache architecture designed with special tracking registers and control logic capable of supporting multiple outstanding cache misses simultaneously without halting other accesses during a prefetch or miss.

Virtual Memory Organization

A system architecture using a Memory Management Unit (MMU) to translate processor-issued virtual addresses into physical addresses for cache and main memory, using disk storage to extend the effective capacity of the memory system.

Translation Lookaside Buffer (TLB)

A high-speed, associative-mapped hardware cache within the MMU that stores recently referenced virtual-to-physical address translation entries (virtual page numbers, control bits, and physical page frames) to accelerate address translation.

Memory-Mapped I/O

An I/O arrangement where I/O device registers share the same address space as main memory, allowing any standard memory-access machine instruction to transfer data to or from an I/O device.

Program-Controlled I/O

A synchronization method in which the processor continuously and repeatedly inspects (polls) a status flag in an I/O interface to determine when the device is ready for data transfer.

Interrupt

A hardware signal sent from an I/O device to the processor over an interrupt-request line to alert the processor that the device requires service, allowing the processor to execute other tasks in the interim.

Interrupt Service Routine (ISR)

The specific software routine executed by the processor in response to an accepted interrupt request from an I/O device.

Interrupt Latency

The total delay between the time an interrupt request is received by the processor and the start of execution of the corresponding interrupt service routine.

Privilege Exception

A specialized interrupt generated when an unauthorized attempt is made to execute a privileged instruction (such as changing the processor priority in the status register) while in user mode.

Polling Scheme (Interrupt Handling)

A method to resolve multiple interrupt sources where the processor sequentially reads the status registers of I/O devices, with priority determined strictly by the order in which devices are inspected.

Daisy Chain Scheme

A hardware arbitration connection where devices share a common interrupt-request line, and an interrupt-acknowledge (INTA) signal propagates serially through the devices, granting priority to the device electrically closest to the processor.

Open-Collector Interrupt Line

A hardware bus configuration where multiple devices attach to an active-low interrupt line ($\overline{\text{INTR}}$) via ground switches with a pull-up resistor connected to $V_{dd}$, producing a wired-OR function: $\text{INTR} = \text{INTR}_1 + \dots + \text{INTR}_n$.

Direct Memory Access (DMA)

A hardware feature where a dedicated DMA controller executes block data transfers directly between an I/O device and main memory without continuous instruction processing by the CPU.

DMA Controller Registers

Dedicated registers within a DMA controller including a Starting Address register, a Word Count register, and a Status and Control register with fields for $\text{R}/\overline{\text{W}}$ (bit $1$), Done (bit $0$), Interrupt Enable (bit $30$), and Interrupt Request (bit $31$).

Cycle Stealing

A DMA operating technique in which the DMA controller temporarily 'steals' individual memory access cycles on the bus from the processor to transfer single words in an interwoven fashion.

Burst Mode (Block Mode)

A DMA transfer mode where the DMA controller is given exclusive control of the bus to transfer an entire block of data contiguously to or from main memory without relinquishing the bus.

Bus Master

The device (processor or DMA controller) that is currently authorized to initiate data transfers on the bus by issuing address and control signals.

Bus Arbitration

The procedure by which the next device to become the bus master is selected and bus mastership is formally transferred, implemented either centrally or in a distributed manner.

Distributed Bus Arbitration

A decentralized bus arbitration scheme where requesting devices transmit their identifier bits onto shared arbitration lines, compare the logical-OR result with their own ID from MSB to LSB, and withdraw lower-order bits upon detecting a difference until the highest-ID device wins.

Synchronous Bus

A bus architecture in which all bus activities and data transfers are synchronized by a shared, periodic clock line, executing fixed-length bus cycles.

Asynchronous Bus

A clockless bus architecture that relies on full handshake signaling (Master-ready and Slave-ready) to coordinate data transfers and automatically accommodate varying device speeds.