Low Power VLSI - Pass Transistor Logic and BDD Synthesis

This set of flashcards covers vocabulary and core concepts related to Pass Transistor Logic (PTL) synthesis and the use of Boolean Decision Diagrams (BDDs) as discussed in the Low Power VLSI lecture.

Pass transistor logic (PTL)

An advanced technique in digital circuit design that implements Boolean functions by using transistors as switches to transfer logic signals directly from input to output, reducing hardware complexity.

Boolean Decision Diagrams (BDDs)

A graphical representation used for the efficient representation and systematic design of Boolean functions, enabling improved power and area efficiency.

Nodes

Components in a Boolean Decision Diagram that represent variables.

Edges

Components in a Boolean Decision Diagram that represent logic values of $0$ and $1$.

Terminal nodes

Nodes in a Boolean Decision Diagram that represent the final output values of $0$ or $1$.

Signal degradation in NMOS

A specific PTL issue where an NMOS transistor passes a strong $0$ but a weak $1$.

Signal degradation in PMOS

A specific PTL issue where a PMOS transistor passes a strong $1$ but a weak $0$.

Threshold voltage drop

An effect where the output voltage reduces when logic $1$ passes through an NMOS transistor, which increases when multiple transistors are cascaded.

Transmission gate (CMOS TG)

An implementation using both NMOS and PMOS transistors to pass both strong $0$ and strong $1$ logic levels.

Shannon's expansion theorem

The mathematical theorem used for BDD construction, expressed as $f(x_1, \text{…}, x_n) = x_i \times f(x_1, \text{…}, 1, \text{…}, x_n) + \bar{x}_i \times f(x_1, \text{…}, 0, \text{…}, x_n)$, where a Boolean function is split based on a variable.

Recursive decomposition

A key feature of Shannon's decomposition that uses shared subtrees to reduce redundancy and ensure efficient storage in BDDs.

Mapping BDD to multiplexers

A synthesis step where each BDD node is converted into one $2:1$ multiplexer, with the variable serving as the select input.

PTL Synthesis Process

A workflow involving converting a Boolean function to a BDD, optimizing the BDD size, mapping nodes to multiplexers, implementing with PTL, and performing post-mapping optimization.

Advantages of PTL with BDD

Includes reduced transistor count, lower power consumption, faster implementation, and better area efficiency, especially for multiplexer-based functions.

Disadvantages of PTL with BDD

Includes threshold voltage drop, weak logic levels, limited chain length, and a lack of automation in standard design flows.