BCA 152 Microprocessor and Computer Architecture Syllabus

Vocabulary flashcards covering key terms, concepts, architectures, instructions, and required readings from the BCA 152 course syllabus.

BCA 152 Course Overview

A 3-credit hour Theory + Lab course (3/3 Hrs workload) designed to familiarize students with fundamental computer architecture, instruction cycles, microprocessor components, Intel 8085, and assembly programming.

Microprocessor Components

The core functional units of a microprocessor system, comprising Registers, Arithmetic Logic Unit (ALU), Control and Timing unit, and System Buses (Address, Data, Control).

Multiplexed Address Data Bus ($AD_0-AD_7$)

A shared set of lines in the Intel 8085 microprocessor used to transfer the lower-order address byte during the initial part of a machine cycle and data during subsequent parts.

Machine Cycle

The sequence of operations required by a microprocessor to access memory or external devices, including Opcode fetch, memory read, and memory write cycles measured in T states.

8085 Data Transfer Instructions

Instructions used to copy data between registers, memory, or I/O ports, including MOV, MVI, STA, LDA, LXI, LDAX, STAX, and XCHG.

8085 Arithmetic Instructions

Instructions that execute mathematical operations on data, including ADD, ADI, ADC, SUB, SUI, SBB, INR, DCR, INX, and DCX.

8085 Logic Instructions

Instructions that perform bitwise logical operations or comparisons, including ANA, ANI, ORA, ORI, XRA, XRI, CMA, and CMP.

8085 Branching Instructions

Instructions that alter sequential program execution conditionally or unconditionally, including JMP, JNZ, JZ, JNC, and JC.

Bus Interface Unit (BIU)

A functional unit in the Intel 8086 microprocessor responsible for handling memory segmentation, fetching instructions, and managing bus operations for the Execution Unit.

Execution Unit (EU)

A functional component of the Intel 8086 microprocessor that decodes instructions, contains registers, and executes instructions sent from the Bus Interface Unit.

Memory Segmentation

The technique used in the 8086 microprocessor to divide memory into distinct logical blocks managed by specific segmentation registers.

Stored Program Organization

A computer architectural model where program instructions and data are stored together in the same primary memory space.

Micro-Operation

An elementary hardware operation performed on data stored in computer registers during a single clock pulse, categorized into arithmetic, logic, and shift micro-operations.

Shift Micro Operations

Operations that shift the bit contents of a register left or right, classified into Logical, Circular, and Arithmetic shift micro-operations.

Control Memory

A specialized memory in a microprogrammed control unit that contains the microprograms consisting of microinstructions.

Hardwired vs Microprogram Control Unit

Hardwired CU uses fixed logic gates and circuits to generate control signals directly, whereas Microprogrammed CU uses microinstruction sequences stored in control memory to execute instructions.

Instruction Formats

The layout of bits in an instruction, classified according to the number of explicit memory/register address fields provided: 3-address, 2-address, 1-address, or 0-address instructions.

RISC vs CISC Architecture

Reduced Instruction Set Computer (RISC) uses a simplified instruction set with optimized pipeline execution, whereas Complex Instruction Set Computer (CISC) uses a rich set of multi-clock instruction formats.

Booth Multiplication

An efficient computer arithmetic algorithm used to multiply two signed binary numbers represented in 2's complement notation.

Isolated vs Memory Mapped I/O

Isolated I/O uses distinct I/O read/write instructions and address space, whereas Memory Mapped I/O assigns regular memory address space to peripheral I/O devices.

Direct Memory Access (DMA)

A technique that enables hardware peripherals to transfer data directly to or from main memory without continuous CPU intervention.

Flynn's Classification

A classification scheme for computer architectures based on the number of concurrent Instruction Streams and Data Streams (SISD, SIMD, MISD, MIMD).

Speed Up Ratio

A metric evaluating pipelining efficiency, defined as the ratio of execution time for a task sequence on a non-pipelined processor to that on a pipelined processor.

Pipeline Hazard

A condition in a pipelined system where the next instruction cannot execute in its designated clock cycle due to data dependency, branch instructions, or hardware resource conflicts.

Gaonkar, R. S. (1998)

Author of the required textbook 'Microprocessor architecture, programming, and applications with the 8085' published by Prentice-Hall, Inc.

Hall, D. V. (1986)

Author of the required textbook 'Microprocessors and interfacing: programming and hardware' published by McGraw-Hill, Inc.

Mano, M. M. (1993)

Author of the required textbook 'Computer system architecture' published by Prentice-Hall, Inc.