VHDL

What items can appear in the declaration region of a VHDL architecture?

Signal declarations, component declarations, and configuration specifications.

Why can’t certain words be used as VHDL entity names?

They are reserved VHDL keywords and cannot be reused as identifiers.

Which VHDL statements are sequential?

if, while, and case statements.

What does an XDC file specify?

FPGA constraints such as pin mappings and timing constraints.

Difference between arrays and records in VHDL?

Arrays contain elements of the same type; records may contain elements of different types.

Give two std_logic metalogical values and meanings.

'Z' means high-impedance; 'X' means unknown.

What does it mean that VHDL is strongly typed?

Types must match exactly and explicit conversions are required.

Range of a 10-bit signed signal?

–512 to +511.

Range of a 10-bit unsigned signal?

0 to 1023.

What does numeric_std provide?

Arithmetic on signed/unsigned types, conversions, and resizing.

What is sign extension?

Extending a signed number by replicating the sign bit to preserve its value.

Sign-extend 10101 and 00001 to 6 bits and add them.

10101→110101, 00001→000001, sum=110110.

When does a process with a sensitivity list execute?

At time zero and whenever any signal in the list changes.

Sensitivity list for a synchronous counter?

Only the clock signal.

Sensitivity list for a combinational multiplexer?

All input signals that affect the output.

Sensitivity list for a D-FF with asynchronous reset?

Clock and reset.

What happens if an if-statement in combinational logic has no else?

A latch is inferred.

What happens if a case statement omits a default branch?

Latches or undefined behaviour may result.

What is component instantiation?

Creating an instance of a component/entity and connecting its ports.

Why instantiate a component in a testbench?

To create the DUT so stimuli can be applied and outputs observed.

Difference between named and positional association?

Positional relies on port order; named explicitly maps each port.

How do you specify which architecture an instance should use?

Use direct entity instantiation with the architecture name.

Are generate statements sequential or concurrent?

Concurrent.

Where can generate statements appear?

In the architecture body.

Can generate bounds depend on signal values?

No, they must be static.

Why use generate statements?

They reduce repetition and improve scalability.

How do you compute the break-even point between ASIC and FPGA?

Solve ASIC_NRE + ASIC_unit_cost×N = FPGA_unit_cost×N.

When is an FPGA more cost-effective?

At low production volumes.

When is an ASIC more cost-effective?

At high production volumes.

Non-cost factors influencing FPGA vs ASIC choice?

Time-to-market, power, performance, flexibility, reliability.

Suitable type for a counter that goes up to 80?

integer range 0 to 80 or unsigned(6 downto 0).

How to convert an integer to two 7-segment digits?

Compute tens=count/10 and units=count mod 10, then map digits to 7-segment patterns.

Signals needed in a car-park counter entity?

clk, rst, car_in, car_out, manual_load, manual_value, tens_seg, units_seg, full_sign, spaces_sign.

Why separate clock generation from other stimuli in a testbench?

It keeps the testbench clean and avoids timing conflicts.

What must a testbench contain?

DUT instantiation, clock process, stimulus process, internal signals.

How to write a 10 ns clock process?

Toggle the clock every 5 ns inside a loop.

How do you count IOBs for an FPGA design?

Count all top-level inputs and outputs.

Example: entity with clk + two 9-bit inputs + two 9-bit outputs → IOB count?

37 IOBs.

How do you assign a specific bit pattern to a signed vector?

Use to_signed(value, width).

How do you retrieve the 5th element of an enumerated type?

Use 'val(4).

Purpose of internal signals in structural VHDL?

To connect component instances inside the architecture.

What is the purpose of a testbench?

To verify design behaviour by applying stimuli and observing outputs.

Why is FPGA preferred when time-to-market is critical?

It requires no fabrication and can be reprogrammed quickly.

What happens if generate statements are replaced with manual instantiation?

Code becomes longer, less scalable, and more error-prone.

What does a configuration specification do?

Selects which architecture a component instance uses.

What causes latch inference in VHDL?

Missing else branches or incomplete case statements in combinational logic.

What is the role of internal carry signals in multi-bit adders/subtractors?

They connect the Cout of one stage to the Cin of the next.

Why must sensitivity lists be complete in combinational logic?

To avoid unintended memory elements.

What is the purpose of the numeric_std resize function?

To change vector width while preserving numeric meaning.

Why is positional association error-prone?

It breaks if the port order changes.

What is the advantage of named association?

It is clearer and safer because each port is explicitly mapped.

What is the purpose of a constraints file?

To map logical ports to physical FPGA pins and define timing constraints.

Why is an FPGA unsuitable for extremely high-volume products?

Its per-unit cost is higher than ASICs.

Why is an ASIC unsuitable for low-volume products?

High NRE costs make it uneconomical.

What is a DUT in a testbench?

The Device Under Test, instantiated inside the testbench.

What is the purpose of a clock enable signal?

It allows a register to update only when enabled.

What is the purpose of an asynchronous reset?

It resets the register immediately, independent of the clock.