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Vocabulary flashcards covering PLC architecture, scan cycles, response time calculations, and digital numbering systems (binary, octal, decimal, hexadecimal, and BCD).
Programmable Logic Controller (PLC)
A microprocessor-based controller that uses programmable memory to store instructions and implement functions such as logic, sequencing, timing, counting, and arithmetic to control machines and industrial processes.
Central Processing Unit (CPU)
The brain of the PLC that reads input signals, retrieves and decodes instructions stored in memory, executes logical and arithmetic operations, and updates output field devices.
Programming Mode
The operating mode of the PLC CPU that accepts and downloads control logic from a personal computer (PC) into PLC memory.
Run Mode
The operating mode of the PLC CPU that actively executes and runs the downloaded control program to operate machinery or a process.
Firmware
Permanent, built-in instructions that govern the PLC's fundamental internal operations and its basic interaction with users and programming interfaces.
User Program
A program created by a user or engineer that specifies the operational logic required to automate a particular machine or process.
Input/Output (I/O) System
The module interface that connects the PLC to physical field devices; the input section receives signals from sensors or switches, while the output section sends signals to actuators, drives, or indicators.
IPO Principle
The three-stage operational concept shared by PLCs and personal computers consisting of Input (receiving sensor data), Processing (evaluating logic within the CPU), and Output (commanding field actuators).

PLC Scan Cycle
The repetitive, sequential operating cycle where the PLC reads inputs, executes the program logic, writes results to outputs, runs self-diagnostics, and performs communications.
Batch Process Mode (Refresh Mode)
An operating method in which a PLC scans and refreshes inputs at the beginning of a cycle, executes program instructions, and updates all outputs simultaneously once per completed scan.
Scan Time
The total duration required for a PLC to complete one full cycle of reading inputs, executing the user ladder program, and writing to outputs, measured in milliseconds (ms) or microseconds (μs).
Best-Case PLC Response Time
The minimum time delay between an input changing and the corresponding output responding, calculated as: Response Time=Input Delay+Minimum Scan Time+Output Delay.
Worst-Case PLC Response Time
The maximum delay between an input signal transition and output activation, occurring when the signal changes just after an input scan and requiring two complete maximum scan cycles: Response Time=Input Delay+(2×Maximum Scan Time)+Output Delay.

Ladder Diagram Elements (1 to 6)
The numbered structural components of a standard ladder logic program: 1 = Power rails, 2 = Rungs, 3 = Normally Open (NO) contacts, 4 = Normally Closed (NC) contacts, 5 = Parallel branch, and 6 = Output coil.
Bit
A single binary digit capable of storing either a 0 or a 1, corresponding to digital OFF/ON or LOW/HIGH states.
Nibble
A digital unit of memory consisting of a group of 4 binary bits.
Byte
A basic unit of computer and PLC memory composed of an 8-bit group.
Word
A larger PLC data unit formed by combining one or more bytes (typically 16 bits or 2 bytes).
Most Significant Bit (MSB)
The leftmost binary digit in a binary number or register, possessing the greatest positional value/weight.
Least Significant Bit (LSB)
The rightmost binary digit in a binary number or register, carrying the lowest positional value (20=1).
Hexadecimal Numbering System
A base-16 numbering system utilizing characters 0–9 and A–F (A=10 through F=15) used to compactly represent long binary strings, memory registers, status words, and fault codes.
Octal Numbering System
A base-8 numbering system that utilizes the digits 0 through 7 to shorten binary numbers.
Binary Coded Decimal (BCD)
A coding system that uses a distinct 4-bit binary group (weighted 8-4-2-1) to represent each decimal digit individually from 0 (00002) to 9 (10012), leaving 4-bit patterns 10102 through 11112 invalid or unused.