COMP 1100: Introduction to Computer Science Flashcards

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Vocabulary flashcards covering Operating Systems, Data Storage, Networking and the Internet, and Data Manipulation based on COMP 1100 lecture materials.

Last updated 8:45 PM on 10/2/26
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70 Terms

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Operating System (OS)

The core software package that coordinates a device's internal activities and oversees its communication with the outside world.

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Batch Processing

An early operating system execution method where user programs (jobs) were collected into a first-in, first-out waiting queue in mass storage and executed sequentially without direct user interaction.

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Multiprogramming

An operating system technique introduced in the late 1950s that keeps the CPU busy by maintaining multiple jobs in main memory at once and switching the CPU to another job when one waits for I/O.

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Time-Sharing

An operating system execution model developed in the early 1960s that allocates small CPU time intervals (time slices) to multiple interactive users via terminals.

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OS Kernel

The fundamental core of an operating system that runs in privileged mode and directly interacts with hardware to provide file, device, memory, and process management services.

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Firmware

Software stored in nonvolatile read-only memory (ROM) that provides low-level control of hardware, such as the Boot Loader that initializes the operating system upon startup.

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Process

The execution of a program, represented by a process state containing the program counter value, CPU register contents, and allocated memory locations.

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Scheduler

An operating system component that tracks all processes in a main memory process table and determines which processes are ready to run.

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Dispatcher

An operating system component that allocates CPU time slices to ready processes and handles context switching when triggered by interrupts.

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Interrupt

A signal sent to the CPU that halts current instruction execution, saves the running process state, and invokes an interrupt handler.

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Context Switch

The procedure during process management where the CPU saves the current state of an executing process and loads the saved state of a new process.

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<p>Deadlock</p>

Deadlock

A condition where two or more processes are permanently blocked because each holds a non-shareable resource while waiting for another resource held by another process.

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Memory Protection

An OS security feature that restricts each running process to its assigned memory space to prevent interference, data corruption, or unauthorized access.

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Privileged Mode

A CPU execution mode permitting execution of all hardware and system instructions, strictly reserved for the operating system kernel.

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Non-Privileged Mode (User Mode)

A restricted CPU execution mode used for application software that prevents direct access to system-critical instructions and hardware without OS intervention.

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System Crash

An OS or application failure caused by internal errors (such as software bugs or hardware malfunctions) resulting in loss of service without compromising system security.

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Security Breach

An incident where an unauthorized attacker bypasses system protection mechanisms to gain unauthorized access to data or resources.

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Bit

Short for binary digit; the fundamental unit of digital information representing a value of either 00 or 11.

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Boolean Operation

An operation acting on Boolean values (True/11 and False/00) to evaluate logical expressions, named after George Boole.

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Truth Table

A table depicting all possible combinations of input values for a Boolean expression alongside their corresponding outputs.

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<p>AND Gate</p>

AND Gate

A logic gate circuit whose output is 11 if and only if all of its input bits are 11.

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<p>OR Gate</p>

OR Gate

A logic gate circuit whose output is 11 if at least one of its input bits is 11.

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<p>XOR Gate</p>

XOR Gate

A logic gate circuit whose output is 11 if an odd number of input bits are 11.

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<p>NOT Gate</p>

NOT Gate

A logic gate circuit with a single input that inverts or flips its input bit value.

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Base (Radix)

The total number of unique symbols or digits used by a number system before advancing to the next place value.

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Hexadecimal Notation

A positional number system with base 1616 that groups binary digits into 4-bit4\text{-bit} nibbles, representing each group with symbols 0−90-9 and A−FA-F.

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<p>Byte</p>

Byte

A continuous sequence of 88 bits, bounded by a most significant bit (MSB) on the left and a least significant bit (LSB) on the right.

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<p>Random Access Memory (RAM)</p>

Random Access Memory (RAM)

Volatile main memory organized into individually addressable cells that can be read or written in any arbitrary order.

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<p>Magnetic Hard Disk Drive (HDD)</p>

Magnetic Hard Disk Drive (HDD)

Non-volatile mass storage device that reads and writes digital data using mechanical read/write heads positioned over rotating magnetic platters.

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<p>Solid State Drive (SSD)</p>

Solid State Drive (SSD)

High-speed, non-volatile storage hardware constructed from semiconductor NAND flash memory chips with no moving mechanical parts.

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<p>Two's Complement Notation</p>

Two's Complement Notation

A fixed-bit encoding system for signed integers where positive numbers have a sign bit of 00, and negative numbers are formed by copying bits from right to left through the first 11, then complementing remaining bits.

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ASCII

American Standard Code for Information Interchange; a 7-bit7\text{-bit} character encoding format assigning unique bit patterns to characters in written English.

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Pixel

Short for picture element; an individual colored dot that serves as the base component in bitmap image representation.

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Lossless Compression

Data reduction methods that compress files while preserving 100%100\% of original data, allowing exact reconstruction upon decompression (e.g., ZIP, PNG, FLAC).

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Lossy Compression

Data reduction methods that permanently eliminate less perceptible information to achieve significantly smaller file sizes (e.g., JPEG, MP3, MP4).

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<p>Parity Bit</p>

Parity Bit

An additional check bit appended to a bit string to ensure the total count of 1s1\text{s} is consistently even or odd, enabling data error detection.

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<p>Bus Topology</p>

Bus Topology

A network configuration where all connected devices share a single main communication line over which broadcasted messages are transmitted.

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<p>Star Topology</p>

Star Topology

A network architecture where every individual computer or device connects directly to a central node, such as a switch or access point.

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Switch

An intelligent network device in a star topology that receives data packets and forwards them specifically to the target recipient device.

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CSMA/CD

Carrier Sense Multiple Access with Collision Detection; a wired bus network protocol where nodes check for channel activity before transmitting and abort transmission if a collision occurs.

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CSMA/CA

Carrier Sense Multiple Access with Collision Avoidance; a wireless network protocol where devices send Request-To-Send (RTS) and Clear-To-Send (CTS) signals to prevent transmission collisions.

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<p>Hidden Terminal Problem</p>

Hidden Terminal Problem

A condition in wireless networking where stations are within range of an Access Point but cannot hear each other, leading to simultaneous transmissions and packet collisions.

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<p>Client-Server Model</p>

Client-Server Model

An interprocess communication architecture where client software applications submit service requests to a centralized server that fulfills them.

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<p>Peer-to-Peer (P2P) Model</p>

Peer-to-Peer (P2P) Model

A decentralized network communication model where participating processes (peers) act as equal partners capable of both requesting and providing resources directly.

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Distributed System

A collection of autonomous, networked computers that coordinate their actions through message passing to operate as a single unified computing facility.

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Cloud Computing

A service model delivering configurable computing resources, data storage, and applications on demand over the Internet using remote server infrastructure.

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Cluster Computing

A high-performance architecture comprising tightly coupled computers located in a single site and managed by a head node to execute parallel computing tasks.

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<p>Tier-1 ISP</p>

Tier-1 ISP

High-capacity telecommunications providers owning the international fiber-optic backbone networks that route global Internet traffic.

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IP Address

A unique numeric identifier assigned to every device connected to an IP network, implemented as 32-bit32\text{-bit} addresses in IPv4 or 128-bit128\text{-bit} addresses in IPv6.

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Domain Name System (DNS)

A distributed network database service that translates human-readable web domain names into numerical IP addresses.

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DHCP

Dynamic Host Configuration Protocol; a network protocol that automatically assigns IP addresses and network configuration settings to devices when they join a network.

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World Wide Web (WWW)

An Internet application infrastructure composed of hyperlinked web pages accessed using URLs and transferred via HTTP/HTTPS protocols.

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URL

Uniform Resource Locator; a standardized string specifying the location protocol, domain, path, and filename of a resource on the Web.

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HTML

HyperText Markup Language; the standard tag-based markup language used to structure text, links, and media content on web pages.

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Firewall

A hardware or software security system that monitors and filters network traffic to block unauthorized access.

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Encryption

The process of scrambling plain text data into an unreadable ciphertext format using cryptographic keys to ensure confidentiality.

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Arithmetic/Logic Unit (ALU)

The subcomponent of a CPU containing digital circuitry that executes arithmetic operations and logical evaluations.

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Control Unit

The CPU component that manages the instruction execution cycle by generating control signals to fetch, decode, and coordinate data movement.

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Register

A small, high-speed temporary storage cell inside the CPU used to hold active data operands, memory addresses, or intermediate results.

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Stored-Program Concept

A computer architecture paradigm where program instructions are encoded as bit patterns and stored in main memory alongside operational data.

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<p>Von Neumann Architecture</p>

Von Neumann Architecture

A standard computer design model based on the stored-program concept, featuring a CPU linked via a shared bus to a main memory unit storing both instructions and data.

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Program Counter

A dedicated CPU register that holds the memory address of the next instruction to be fetched and executed.

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Instruction Set Architecture (ISA)

The abstract boundary defining a CPU's supported machine language operations, registers, data types, and instruction bit encodings.

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<p>Op-Code</p>

Op-Code

The operation code portion of a machine language instruction that specifies the fundamental CPU operation (such as STORE or ADD) to perform.

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RISC

Reduced Instruction Set Computer; a CPU design philosophy focused on executing a minimal, highly optimized set of instructions for fast, energy-efficient processing.

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CISC

Complex Instruction Set Computer; a CPU design philosophy incorporating a large set of complex instructions capable of executing multi-step operations in fewer instruction lines.

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<p>Multicore Processor</p>

Multicore Processor

A single integrated circuit chip containing two or more complete independent processing cores capable of true parallel instruction execution.

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Serial Communication

A data transmission method where bit signals are sent sequentially one at a time over a single channel or physical wire.

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Parallel Communication

A data transmission method where multiple bit signals are sent simultaneously over parallel physical wires or channels.

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Handshaking

A signaling exchange protocol between a CPU and an I/O device verifying mutual readiness before data transfer begins.