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What is the target triple riscv32-unknown-elf-gcc?
Architecture: 32-bit RISC-V
OS: unknown (bare metal, no OS)
Format: ELF (Executable and Linkable Format)
What happens when you flash a UF2 built for ARM onto a RISC-V core?
Both UF2 files structurally valid (identical wrapping)
Instructions inside are gibberish to wrong core
Core hits undefined opcodes almost immediately and faults
Manifests as "boots but nothing happens"
Why can't system gcc compile code for the Pico?
System gcc produces binaries for host architecture (x86-64 on Mac)
Pico RP2350 executes 32-bit RISC-V instructions in bare-metal ELF format
Cross-compiler needed: backend emits RISC-V machine code, linker uses Pico's flash/SRAM map, minimal C library (newlib-nano)
Why does BOOTSEL recovery work even after bad firmware flash?
USB mass-storage flashing implemented in ROM bootloader (not user-programmable flash)
ROM physically unwriteable after manufacture (no user firmware can corrupt it)
Bootloader checks BOOTSEL pin before any user code executes, skips loading user firmware if pulled low
Why does fgets() fail with '_impure_ptr undefined' on embedded target?
Embedded C libraries (newlib-nano) omit reentrant stdio to save flash/RAM
Header declares fgets (compilation succeeds) but symbol _impure_ptr cannot be resolved at link time
Fix: use lower-level routines wired directly to platform's serial driver (e.g., getchar())
What is the lost initial output problem?
main() begins within milliseconds of power-on, but USB host enumeration takes substantially longer
Output during this window sent into buffer host never reads (dropped)
Fix: wait for stdio_usb_connected() before producing output
What are three advantages of Python for embedded development?
Interactive REPL: test without compile-flash cycle (minutes per iteration)
Garbage collection: removes use-after-free, double-free, memory leaks
High-level built-ins: dictionaries, list comprehensions, JSON/hex/base64 decoders
What are three limitations of Python for embedded development?
Interpreter footprint: MicroPython binary ~1MB flash (substantial fraction of typical storage)
Execution speed: bytecode 1-2 orders of magnitude slower than compiled C
Library subset: embedded ports implement only portion of CPython standard library
What is the reasoning behind two-language workflow (MicroPython then C)?
One-off tasks (discovering MAC address): iteration cost dominates (C would need build, compile, flash)
MicroPython collapses to few seconds of interactive REPL work
Production firmware needs predictable timing and fixed memory budget (C is right tool)
Why can reading entire HTTP response into RAM buffer fail on microcontroller?
Total response size unknown in advance (may exceed available RAM)
Reserving worst-case buffer wastes RAM; dynamic allocation risks unrecoverable malloc failure
Alternative: stream processing (state machine consumes bytes as they arrive, bounded RAM usage independent of response size)
How is dynamic web content served without filesystem on Pico?
Build time: tool converts HTML template to C byte array compiled into firmware (placeholders like )
Run time: HTTP server transmits byte array; when placeholder encountered, registered C function called; return string sent in place of tag
Why not use real filesystem to serve files on Pico?
Adding filesystem requires implementation code, wear-levelling logic, upload mechanism (complexity for little benefit)
Served pages rarely change → baking into binary costs only actual content
Filesystem worthwhile only when content must be writable at run time (logs, user uploads, persistent config)
What are three approaches to obtain wall-clock time on device with no RTC and no battery?
Hard-code constant at compile time (trivial, wrong from first reboot, only viable for relative time within session)
Synchronise from network on every boot (NTP) (requires network connectivity, standard for internet-connected devices)
Add external RTC IC with coin-cell battery (keeps time across power cycles, adds component cost and battery replacement)
Why do NTP and HTTP use different ports (123 vs 80)?
Ports identify service at given IP address, allowing single host to offer multiple services simultaneously
NTP runs over UDP (connectionless, low overhead); HTTP over TCP (reliable, ordered)
Consequence: supporting both requires two distinct connection setups and parsers (device needing only time can omit HTTP stack)
Why is disabling interrupts insufficient for critical sections on dual-core?
On single-core: disabling interrupts sufficient (only way other code runs is via interrupt)
On dual-core: two tasks may run on two cores simultaneously, each core's interrupt mask independent
RTOS for multi-core uses hardware spinlock (atomic test-and-set) with local interrupt disable (protects against preemption on current core and concurrent execution on other core)
Why does printf from two cores produce garbled output?
printf is not reentrant (walks format string, writes to shared output buffer, updates global state)
Two tasks calling concurrently on different cores modify shared state simultaneously
Fixes: wrap printf in critical section, give each task own output channel, or use reentrant logging primitive
What are three ways to make global state survive reboot?
Write to on-board flash (data survives indefinitely, limitation: finite erase cycles ~100,000)
Write to external EEPROM over I2C (byte-addressable, millions of write cycles, limitation: slower, requires additional component)
Write to SD card with FAT filesystem (large capacity, removable, limitation: requires KB of RAM, slow initialisation)
What happens when writing to flash on every keystroke?
Flash memory endures only limited erase cycles per block (~100,000)
Writing every keystroke exhausts wear budget in weeks
Fixes: batch writes (touch flash every few seconds), wear-levelling filesystem (LittleFS), move to EEPROM, or RAM buffer with deferred write