Hardware Security Day 4 – Physical Attacks, Fault Injection, and Secure Boot

Weeks 9–10 and the Week 3 VoltPillager case study. Compare physical attack categories, explain how glitches can cause hardware faults, and practice connecting each fault to its security impact and a matching defense.

Physical attack

A hardware security attack that uses physical access or interaction to observe a device or interfere with its operation.

Non-invasive attack

Uses external interfaces or measurements while leaving the chip package intact. External power measurement is an example.

Semi-invasive attack

Exposes the die and interacts with it without direct electrical contact with internal circuitry. Optical fault injection is an example.

Invasive attack

Directly probes or modifies structures inside a chip. Microprobing and focused ion beam edits are examples.

Decapsulation

Opening or removing a chip's protective package to expose the die.

Deprocessing

Removing layers from an exposed chip to reveal internal structures.

Microprobing

Using a fine probe to make electrical contact with an internal chip node for measurement or manipulation.

Focused ion beam (FIB)

A tool that uses a focused beam of ions to remove material or modify structures within a chip.

Fault injection

Deliberately disturbing a device so that it produces an incorrect result or changes its state or control flow.

Fault injection vs. side-channel observation

Fault injection changes device behavior. Side-channel observation infers information from effects the device produces during operation.

Glitch

A brief disturbance in a physical condition such as clock timing or supply voltage.

Clock glitch

A brief clock disturbance that can leave a circuit too little time to finish a computation before its result is captured.

Voltage glitch

A brief change in supply voltage that can disrupt circuit operation. Undervolting can slow switching enough to cause timing errors.

Optical fault injection

Using a pulse of light to disturb circuitry in a localized region of a chip.

Timing violation

A signal arrives too late or changes too close to the moment it is captured. The circuit may record the wrong value.

Fault model

A description of the effect a disturbance has on computation. Examples include a bit flip or an instruction skip.

Bit flip

A fault that changes a bit from 0 to 1 or from 1 to 0.

Instruction skip

A fault effect in which an instruction fails to execute as expected. Skipping a branch can change which code runs next.

Delayed-write fault

A write reaches its destination later than expected. A later operation may observe an old value.

Physical method vs. fault model vs. security impact

A voltage glitch is a physical method. An instruction skip is a possible fault model. Failure to enforce a security check is a possible impact.

Why a glitch can have different outcomes

The effect depends on which operation is active and how the device responds. The device may continue normally or crash or produce a fault.

Secure boot

A boot process in which a trusted stage verifies the next stage before allowing it to run.

Hardware root of trust

A trusted hardware-backed starting point for security decisions such as verifying the first boot stage.

Chain of trust

Each trusted boot stage verifies the next stage before transferring control to it.

Signature verification in secure boot

A check that the image was signed by an authorized signer and has remained intact since signing.

Verification vs. enforcement

Verification determines whether an image is valid. Enforcement uses that result to decide whether execution is permitted.

Secure boot control-flow fault

A fault can disrupt enforcement even when signature verification correctly detects an invalid image.

Fail-closed behavior

The device blocks boot or halts safely if verification fails or its result cannot be trusted.

Redundant verification

Repeating a security check or checking its result independently so a single fault is less likely to cause unsafe execution.

Common-mode fault

A single disturbance affects multiple safeguards in the same way. Identical redundant checks can therefore fail together.

Fault sensor

Hardware that detects conditions such as abnormal voltage or clock behavior and can trigger a protective response.

Control-flow hardening

Designing critical code so that a skipped instruction or branch is less likely to permit an unauthorized action.

Intel SGX enclave

A protected execution environment designed to isolate code and data from other software on the system.

Voltage regulator

A component that supplies and adjusts the voltage delivered to the processor.

Serial Voltage Identification (SVID)

The communication interface between the processor and its voltage regulator discussed in the VoltPillager case.

VoltPillager

A board-level case study showing that hardware undervolting through the SVID path can induce faults in computations running inside Intel SGX enclaves.

Plundervolt

A case study showing that software-controlled undervolting can induce faults in Intel SGX computations.

VoltPillager vs. Plundervolt

VoltPillager targets the board-level voltage control path. Plundervolt uses a software-accessible voltage control path.

VoltPillager defense lesson

Restricting software voltage controls addresses the software path. Board-level access to the regulator interface is a separate part of the threat model.