ENEL 453 Practice Questions Part 2

What distinguishes sequential circuits from combinational ones?

Sequential logic stores and updates its state based on input and clock

In SystemVerilog, what does the keyword always_ff indicate?

A block that implies flip-flops

Which statement is most accurate?

module blip(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (reset) q <= 4'b0;
        else q <= d;
endmodule

D flip-flop with synchronous reset

What changes if posedge reset is removed from the sensitivity list?

module flopr(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk, posedge reset)
        if (reset) q <= 4'b0;
        else q <= d;
endmodule

The reset would be applied synchronously with the clock

What is the purpose of a reset signal in sequential logic circuits?

To initialize flip-flops to a known state

Which of the following is true about an asynchronous reset in SystemVerilog?

It takes effect immediately, independent of the clock

Consider the following code. What type of reset does this describe?

module flopr(input logic clk, input logic reset_n, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk, negedge reset_n)
        if (!reset_n) q <= 4'b0;
        else q <= d;
endmodule

Asynchronous, active-low reset

In the following code, what does @(posedge clk) do?

module flopr(input logic clk, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        q <= d;
endmodule

It triggers the logic only on the rising clock edge of the clock

Which of the following describes the flip-flop reset?

module flopr(input logic clk, input logic reset_n, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (!reset_n) q <= 4'b0;
        else q <= d;
endmodule

Synchronous, active-low reset

Why is it important to avoid using latches in hardware design?

Latches can lead to timing issues and metastability

What does the following code snippet implement?

module ff(input logic clk, input logic reset, input logic en, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (reset) q <= 4'b0;
        else if (en) q <= d;
endmodule

Flip-flop with synchronous reset and enable

What is the effect of using <= in the following code?

module flop(input logic clk, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        q <= d;
endmodule

It creates a non-blocking assignment

In SystemVerilog, what is the function of always_comb?

To create a combinational block

What can go wrong if a register has NO reset?

The flip-flop may power up in an unknown state

What does a reset sampled at the clock edge gain over one that is not?

Synchronous reset avoids glitches and metastability

What does an n_suffix on a name such as reset_n conventionally indicate?

It denotes that the reset is active when the signal is low

Which of the following is true about this flip-flop?

module flop(input logic clk, input logic en, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (en) q <= d;
endmodule

The flip-flop updates the output q only when en is high

In the context of sequential logic design, what is an idiom?

A common coding pattern that signifies a specific hardware structure

What is the primary difference between a flip-flop and a latch?

Flip-flops are edge-triggered, while latches are level-sensitive

Which SystemVerilog keyword is recommended for modeling combinational logic?

always_comb

What is the purpose of a synchronizer in digital design?

To convert an asynchronous input into a synchronous signal, reducing the risk of metastability

Which of the following describes a potential consequence of violating setup or hold time constraints in a flip-flop?

Metastability

In the context of synchronous design, what does the term 'cyclic path' refer to, if it is properly designed?

A path that includes at least one register and has feedback

What is the significance of the sensitivity list in an always_ff block?

It lists the signals that trigger the block's execution

What is the key advantage of using synchronous reset over asynchronous reset in flip-flops?

Asynchronous resets are more susceptible to metastability issues

For an enabled flip-flop with an asynchronous reset, under what condition does the output HOLD its previous value?

module flopren (input  logic       clk,
               input  logic       reset,
               input  logic       en,
               input  logic [3:0] d,
               output logic [3:0] q);
  // enable and active-high asynchronous reset
  always_ff @(posedge clk, posedge reset)
    if      (reset) q <= 4'b0;
    else if (en)    q <= d;
endmodule

When reset and en are both low

What is the primary reason for using a two (or more) flip-flop synchronizer for asynchronous inputs?

To mitigate the risk of metastability

What is the hazard when an asynchronous reset is DE-ASSERTED close to a clock edge?

It can cause metastability

Why is it generally recommended to include a small time offset (e.g., CLK_PERIOD/4) in testbench stimulus?

To make waveforms easier to interpret by separating signal changes from clock edges

Which coding practice is most suitable for describing flip-flops in SystemVerilog?

Using always_ff blocks with non-blocking assignments (<=)

Why are latches generally discouraged in synchronous designs?

Their level-sensitive behavior can lead to timing issues and metastability

Analyze the following SystemVerilog code:

always_ff @(posedge clk)
  if (reset)
    q <= 4'b0;
  else
    q <= d;

Which statement best describes the reset behavior in this code?

Synchronous, active-high reset

Consider this SystemVerilog code snippet:

always_ff @(posedge clk, negedge reset_n)
  if (!reset_n)
    q <= 4'b0;
  else
    q <= d;

What type of reset is implemented in this flip-flop?

Asynchronous, active-low

When must a procedural block be wrapped in begin and end?

When it contains more than one statement

What can go wrong in an ASIC if registers are left without a reset?

What can go wrong in an ASIC if registers are left without a reset

You encounter the following SystemVerilog code in a design:

logic [7:0] data_out;
always_ff @(posedge clk)
  data_out <= {data_out[6:0], data_in};

What functionality does this code most likely implement?

An 8-bit shift register

Which SystemVerilog construct, used without a loop statement, creates a repetitive clock signal in a testbench?

always

Which of the following statements about the $display task in SystemVerilog is FALSE?

It automatically stops the simulation after printing a message

What type of circuit does the following SystemVerilog code describe?

module blob(input logic en, input logic [3:0] d, output logic [3:0] q);
    always @(*)
        if (en) q = d;
endmodule

Latch

What does the following SystemVerilog code implement?

module bleeb(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk or posedge reset)
        if (reset) q <= 4'b0;
        else q <= d;
endmodule

Positive-edge triggered D flip-flop with asynchronous reset

Which of the following represents the behavior of the code below?

module ff2(input logic clk, input logic en, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (en) q <= d;
endmodule

The flip-flop updates q on the positive edge of the clock only if en is high

What type of reset is implemented in the following SystemVerilog code?

module flopr(input logic clk, input logic reset_n, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk or negedge reset_n)
        if (reset_n) q <= 4'b0;
        else q <= d;
endmodule	

None because the code has an error

What does the following SystemVerilog code do?

module flopr(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk or posedge reset)
        if (reset) q <= 4'b0;
        else q <= d;
endmodule

Sets q to zero when reset is high and updates q on the rising clock edge

In the SystemVerilog code below, the input d comes from a push-button and is asynchronous to clk. Which of the following is true about this code?

module bean(input logic clk, input logic d, output logic q);
    logic n1;
    always_ff @(posedge clk)
        n1 <= d;
    always_ff @(posedge clk)
        q <= n1;
endmodule

This is a synchronizer to handle asynchronous inputs

Which scenario is MOST likely to cause metastability in a flip-flop?

The data input changes near the clock edge, within the setup and hold time window

What is the primary purpose of synchronous design principles?

To reduce the risk of metastability

Which of the following statements about metastability is TRUE?

The output may hover between valid levels before settling

In the context of synchronous design, what is a "cyclic path"?

A signal path that passes through at least one flip-flop and feeds back to its origin

What is the most effective way to keep metastability from reaching the rest of a digital system?

Synchronize asynchronous inputs using multiple flip-flops in series

In the following synchronizer code, how does it help mitigate metastability?

module sync(input logic clk, input logic d, output logic q);
    logic n1;
    always_ff @(posedge clk)
        n1 <= d;
    always_ff @(posedge clk)
        q <= n1;
endmodule

Two flip-flops in series give the signal time to settle

What is a synchronous design in digital circuits?

A design where all flip-flops share the same clock signal

How does using a synchronous reset in flip-flops help improve metastability tolerance?

It ensures the reset signal is sampled with the clock, avoiding asynchronous input changes

How does a setup violation relate to metastability?

Setup time violations make a metastable output more likely

What does clock skew do to a synchronous design?

Skew creates timing differences between flip-flops

Why is it important to ensure that all registers in a synchronous design share the same clock signal?

To prevent data corruption caused by clock domain crossings

Which of the following is a benefit of synchronous design over asynchronous design?

Synchronous designs are easier to test and verify

What is the primary reason for avoiding combinational feedback loops in synchronous designs?

They can lead to unpredictable oscillations and glitches

Which of the following techniques is NOT typically used to mitigate metastability issues in digital designs?

Increasing the clock frequency

Consider a flip-flop with a setup time of 2 ns and a hold time of 1 ns. If the data input changes 1.5 ns before the clock edge, which scenario is most likely to occur?

The flip-flop's output may become metastable

How does raising the clock rate change the chance of a flip-flop going metastable?

Metastability is more likely to occur at higher clock frequencies

Reviewing this code, what is the problem?

always_ff @(posedge clk) begin
  if (async_in)
    q <= 1'b1;
end

It samples async_in without a synchronizer

In the context of metastability, what does the term "resolution time" refer to?

The time required for a metastable signal to settle to a valid logic level

What is wrong with this code?

logic sig_a, sig_b;
always_ff @(posedge clk_a)
  sig_a <= in_a;
always_ff @(posedge clk_b)
  sig_b <= sig_a;

It crosses clock domains with no synchronizer

Which of the following statements about synchronous design is FALSE?

Combinational feedback loops are generally acceptable in synchronous designs

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,
  input  logic [3:0] d,
  output logic [3:0] y
);
  always_ff@(posedge clk)
    y <= d;
endmodule

d = 0;
#15;
#20 d = 12;
#20 d = 12;
#20 d = 12;
#20 d = 12;
#20 d = 12;
#20 d = 12;
#20 d = 4;
#20 d = 4;
#20 d = 4;
#20 d = 5;

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,
  input  logic [3:0] d,
  output logic [3:0] y
);
  always_ff@(posedge clk)
    y <= d;
endmodule

d = 0;
#15;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 13;

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock, reset and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,reset,
  input  logic [3:0] d,
  output logic [3:0] q
);
  always_ff@(posedge clk, posedge reset)
    if (reset)
      q <= 4'b0;
    else
      q <= d;
endmodule

reset = 1;
d = 0;
#15;
#40 reset = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock, reset and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,reset,
  input  logic [3:0] d,
  output logic [3:0] q
);
  always_ff@(posedge clk, posedge reset)
    if (reset)
      q <= 4'b0;
    else
      q <= d;
endmodule

reset = 1;
d = 0;
#15;
#40 reset = 0;
#20 d = 0;
#20 d = 0;
#20 d = 0;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 2;
#20 d = 13;

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock, reset and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,reset,en,
  input  logic [3:0] d,
  output logic [3:0] q
);
  always_ff@(posedge clk,posedge reset)
    if (reset)
      q <= 4'b0;
    else if (en)
      q <= d;
endmodule

reset = 1;
en = 0;
d = 0;
#15;
#40 reset = 0;
#20 en = 1;  d = 4;
#20 en = 1;  d = 4;
#20 en = 1;  d = 4;
#20 en = 0;  d = 1;
#20 en = 0;  d = 1;
#20 en = 0;  d = 1;
#20 en = 1;  d = 9;
#20 en = 0;  d = 9;
#20 en = 0;  d = 9;
#20 en = 1;  d = 1;

The SystemVerilog module below was simulated, producing the timing diagram shown. Which testbench stimulus produced it? The diagram shows the clock, reset and the module's outputs; the other inputs are not drawn, so work out what each stimulus would make the outputs do.

module dut(
  input  logic       clk,reset,en,
  input  logic [3:0] d,
  output logic [3:0] q
);
  always_ff@(posedge clk,posedge reset)
    if (reset)
      q <= 4'b0;
    else if (en)
      q <= d;
endmodule

reset = 1;
en = 0;
d = 0;
#15;
#40 reset = 0;
#20 en = 1;  d = 7;
#20 en = 0;  d = 7;
#20 en = 0;  d = 7;
#20 en = 0;  d = 0;
#20 en = 1;  d = 0;
#20 en = 1;  d = 0;
#20 en = 0;  d = 11;
#20 en = 1;  d = 11;
#20 en = 0;  d = 11;
#20 en = 1;  d = 8;

What should be included in the sensitivity list of an always_ff block for a clocked flip-flop with an asynchronous reset?

Both clock and reset

What is wrong with the following code that tries to describe a D flip-flop with synchronous reset?

module flopr(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q);
    always_ff @(posedge clk)
        if (reset) q <= 4'b0;
        else d <= q;
endmodule

The assignment d <= q is incorrect, it should be q <= d

What is the main advantage of using behavioral simulation in FPGA design?

It provides a quick, high-level functional check of the HDL code

Which of the following describes a post-synthesis functional simulation?

A simulation that ignores hardware timing but verifies logic implementation

Which stage of the flow gives the most faithful picture of real timing?

Post-implementation timing simulation

Which effects does post-implementation timing simulation model?

Hardware placement and routing delays

What is one major reason that post-synthesis functional simulations might fail even though the behavioral simulation passes?

A mismatch between RTL code and hardware implementation

Which start-up delay must a testbench wait out at time zero in post-synthesis and post-implementation simulations, but NOT in behavioral simulation?

Global set/reset delay (GSR)

In the Xilinx Vivado environment, what is the purpose of adding a 100 ns delay at the start of a testbench during post-synthesis and post-implementation simulations?

To allow time for the FPGA's global set/reset signal to stabilize

Which of the following types of simulation provides the fastest execution time but least accurate hardware modeling?

Behavioral simulation

Why run a timing simulation immediately after synthesis rather than waiting?

It provides early detection of potential timing issues after synthesis

Which statement about the fastest simulation stage is true?

Behavioral simulation does not account for hardware timing and placement

What can be inferred if a design passes behavioral simulation but fails post-synthesis functional simulation?

There is a mismatch between the design and the hardware implementation

What does post-implementation timing simulation model that post-synthesis simulation does not?

Exact placement and routing delays

What is a post-implementation functional simulation primarily used for?

Ensuring that the hardware meets functional specifications

In a post-implementation timing simulation, what does the modelled clock buffer (BUFG) propagation delay represent?

The time the clock takes to cross the distribution network

What is one reason that post-implementation timing simulation is slower than other simulation types?

It includes propagation delays through hardware buffers and routing

In a behavioral simulation, how are hardware resources such as flip-flops and lookup tables treated?

No FPGA primitives are involved: the RTL is simulated as written

In a typical FPGA design flow, why would a designer run post-implementation timing simulation after post-synthesis functional simulation?

To validate the design's functionality with actual hardware timing and placement

Which simulation runs directly on the HDL source, before synthesis, and ignores hardware timing?

Behavioral simulation

What do the Xilinx IBUF and BUFG primitives do?

They buffer the clock and distribute it with low skew

A testbench used for post-synthesis and post-implementation simulation omits the 100 ns start-up delay shown below. What is the likely result?

initial begin
  reset = 0;
  #100; // Delay for GSR
  // ... rest of the testbench code
end

The simulations would run, but stimulus applied during the global set/reset would be ignored, so the results may not match the hardware

How do a simulation's fidelity and its run time relate?

The final timing stage is the most faithful and the slowest

What is the main advantage of using a Gray code sequence in digital designs, as demonstrated in the Gray code generator example?

It minimizes the number of bit transitions between consecutive values, reducing the likelihood of glitches

Which of the following design practices can help improve the portability of SystemVerilog testbench code across different simulation types (behavioral, post-synthesis, post-implementation)?

Including the GSR delay even for behavioral simulations

Consider the following SystemVerilog code snippet:

logic [3:0] data_in;
logic [7:0] data_out;
assign data_out = {data_in, 4'b0000};

Which SystemVerilog operator is used on data_in to form data_out?

Concatenation

In the SystemVerilog testbench for the Gray code generator, the clock signal is generated using the following code:

always begin
  #(CLK_PERIOD / 2) clk = 0;
  #(CLK_PERIOD / 2) clk = 1;
end

If you want to double the clock frequency, how should you modify the code?

Change CLK_PERIOD / 2 to CLK_PERIOD / 4 in both lines

Analyze the following SystemVerilog code snippet:

logic [7:0] a = 8'b10101010;
logic [3:0] b;
assign b = a[7:4] ^ a[3:0];

What will be the value of signal b after this code executes?

4'b0000

A design simulates correctly at every stage, is programmed onto the board, and misbehaves only when a particular input arrives asynchronously. Which stage would most likely have exposed this?

None of them reliably; the fault depends on timing the simulator cannot predict

A team is iterating quickly on the logic of a design, running the full test suite after every edit. Which simulation stage should they use for that loop?

Behavioural, because it is fastest and the logic is what is changing