Types of Primary Memory

0.0(0)
Studied by 0 people
call kaiCall Kai
learnLearn
examPractice Test
spaced repetitionSpaced Repetition
heart puzzleMatch
flashcardsFlashcards
GameKnowt Play
Card Sorting

1/19

flashcard set

Earn XP

Description and Tags

A1.1.4

Last updated 12:28 PM on 10/15/26
Name
Mastery
Learn
Test
Matching
Spaced
Call with Kai
Chat

No analytics yet

Send a link to your students to track their progress

20 Terms

1
New cards

What is primary memory?

  • The central workspace for the CPU

  • Facilitates the storage and quick access to data and instructions which are in active use


2
New cards

What is volatile memory?

  • Requires power to maintain the stored data

  • When power is turned off, the data is lost

e.g. random access memory (RAM)


3
New cards

What is non-volatile memory?

  • Retains stored information when when the power is turned off

e.g. read-only memory (ROM), solid state drives (SSDs), and hard disk drives (HDDs)


4
New cards

What are the 4 types of primary memory

  • Registers

  • Cache (L1, L2, L3)


5
New cards

What are registers?

  • The fastest and smallest type of memory

  • Built directly into the CPU

  • Store data, instructions, addresses the CPU is actively executing

  • Volatile

  • The fundamental unit of data handled by a CPU’s architecture is the “word size”, which describes the size of the register

  • 32 or 64 bits of data


6
New cards

What is cache?

  • High-speed memory

  • On or close to the CPU

  • Caches bridge the speed gap between registers and ram

  • Hold frequently used data and instructions for quick retrieval

  • Volatile


7
New cards

What are the 3 types of cache?

L1, L2, and L3

8
New cards

What is L1 cache?

  • Typically ranges from 32 KB to 256 KB per core, with data and instructions caches are separate in some architectures


9
New cards

What is L2 cache?

  • Typically ranges from 256 KB - 16 MB per core or shared across multiple cores


10
New cards

What is L3 cache?

  • Typically ranges from 2 MB to 32 MB shared across all cores in a CPU


11
New cards

What is RAM?

  • aka Random access memory

  • Primary workspace of the computer

  • Temporarily store currently running operating system, processes, and active data and instructions

  • Volatile

  • Capacity measured in gigabytes (GB)


12
New cards

What is ROM?

  • aka Read-only memory

  • Non-volatile

  • Stores essential instructions and data for the computer to start up (system boot-up and low level start up operations)

  • Data in ROM is typically not modifiable during normal computer operation

  • ROM’s role is primarily for firmware storage


13
New cards

What is latency?

aka lag

The time delay between the transmission of a data packet and its reception

Measured in millisecond

Represents the total time taken for data to travel from the source to the destination

14
New cards

How does CPU interact with the registers?

  • Direct interaction

    • The CPU interacts directly with the registers which are used to store immediate data that the CPU needs for current operations

  • Optimization

    • By using registers for the most imediate neccesary data and instructions, the CPU minimizes the need to access slower types of memory signifcantly speeding up the processing time


15
New cards

How does CPU interact with the cache?

  • Hierarchical use

    • Cache memory serves as a high-speed intermediary between the CPU and the slower main memory (RAM). It is divided into 3 levels (L1, L2, L3) based on the proximity to the CPU, with L1 being the smallest and fastest and L3 being larger and slightly slower but still faster than RAM.

  • Data and instructions prefetching

    • Modern CPUs use sophisticated algorithms to predict when data and instructions will be needed soon, and pre-emptively load them into the cache. This anticipatory action reduces the time the CPU speds witing for data, thus optimizing performance

  • Spatial and temporal locality

    • Caches exploit the principles of spatial (data near recently accessed data is likely to be accessed soon) locality to keep relevant data close at hand, further optimizing performance


16
New cards

How does CPU interact with the RAM?

  • Central data repository

    • RAM holds the operating system, applications and data that are currently in use. It provides a much larger space for data storage compared to cache and registers

  • Interaction through memory controller

    • The CPU interacts with RAM via the memory controller, a chipset that manages data transactions between the CPU and RAM. This controller plays a critical role in managing access times and optimizing the flow of data between the CPU and RAM

  • Virtual memory

    • The system can use a portion of the hard drive (or SSD) as virtual memory, extending the available memory space. The CPU manages the swapping of data between RAM and virtual memory, though this process is significantly slower than accessing RAM directly


17
New cards

How does CPU interact with the ROM?

  • Boot-up process

    • While not directly involved in the CPU’s data processing tasks, ROM contains the firmware or BIOS necessary for the initial booting of the computer and basic hardware intialization. The CPU accesses the read only data at start up to load the operating system form secondary storage (e.g. HDD or SSD) into RAM


18
New cards

What does cache hit mean?

CPU finds the data it needs

  • Fastest case as the CPU can access the data almost instantaneously


19
New cards

What does cache miss mean?

CPU does not find the data it needs

  • Slowest case as the CPU needs to fetch data from RAM which is slower than accessing from cache


20
New cards

What are 3 ways to minimize cache misses?

  • Prefetching

    • The CPU can predict which data it will need in the future and fetch it into cache before it is actually needed

  • Memory allocation

    • The operating system can allocate data to appropriate memory locations based on usage patterns to maximize cache hits

  • Cache replacement policies

    • The operating systems can choose which data to evict from the cache when it is full to optimize cache hit rates