EGCP-3010 - Evita VHDL T/F Questions

Entity supports a name for a system and specification of its connections only.

False

Structural specifications can be hierarchical.

True

An object declared in a package can be used if the package is located in the same directory or folder as the entity.

False

The only two types of design units are entities and architectures.

False

Inputs to a system are called generics and outputs - ports.

False

Behavioral specification supports explicitly what building blocks are needed to synthesize particular system.

False

One entity can be assigned to many architectures.

True

Each system has to have an interface.

True

In order to use the Standard package an entity must be preceded by library and use clauses.

False

Each system specified in VHDL is a composition of an entity and an architecture.

True

A package is a compact way of writing an entity-architecture pair to disk.

False

Entity is of primary importance for a VHDL system.

True

Architecture is specified with respect to an entity.

True

One architecture can be assigned to many entities.

False

Behavioral synthesis is easier than structural.

False

An eight-bit bus is represented by a standard type byte.

False

Signals that connect the system with its environment are specified as ports.

True

Bus width is implicitly defined by the bit order in the definition.

True

It is possible to check previous values of VHDL signals.

True

The order of bits specified in a vector is not important.

False

Signals internal to the system are specified as generics in the entity, because they have to be generated.

False

Declaration of an internal signal contains the name of the signal, its mode and type.

False

Signals can be defined as carriers of information.

True

If a signal is declared in a package, which is used by an entity, then the use clause must be applied in architectures of this entity as well.

False

The only signals in electrical devices (e.g. computers) are electrical signals.

False

All signals declared in an entity are visible in all architectures assigned to this entity.

True

Bus and vector are two names of the same concept.

True

Left bound of the order of bits in a vector must always be smaller than the right bound.

False

Each port must be specified with a mode.

True

All signals of a system are defined in the system's entity.

False

Entity name can appear after the end entity clause.

True

A port must be either input or output.

False

Generics can be dynamically changed during simulation of the code.

False

Comments start and end with a double hyphen (--).

False

Ports are static communication links between the entity and its environment.

False

A port mode specifies the information about the direction of data flow through the port.

True

Generics support static input values to the entity from its environment.

True

VHDL is a case-sensitive language.

False

Generics can be used for specifications of ports (e.g. bus width) in the same entity.

True

No identifiers in VHDL may contain spaces.

True

Each generic must be specified together with a mode.

False

An entity can be terminated with an end; clause.

True

Ports are signals.

True

Describing each port with a comment at the end of line is required by the VHDL Language Standard.

False

It is allowed to specify initial value of a port.

True

The value of a complete vector should be written in double quotes and the value of its slice in single quotes.

False

The signal assignment sign can be oriented either to the left or to the right (<= or =>) according to the needs of a designer.

False

Constants can be used in expressions.

True

Set of states of a Finite State Machine is usually declared as an enumeration type.

True

All elements of an array must be of the same type.

True

Multiplication of a real number by an integer is allowed in VHDL.

False

If an impulse on a signal line is wider than the delay, an inertial delay model and a transport delay model will give exactly the same results.

True

Scalar types are specified using either range or enumeration of their elements.

True

A constant can be assigned a new value if the new value is equal to the previous one.

False

Boolean true is equivalent of bit '1'.

False

When a constant is declared, it is enough to specify its value because its type is implicitly determined from the value.

False

Physical type values are synthesizable if they are of standard time type.

False

Operators are always defined for particular types.

True

Inertial delay is the default delay mode in VHDL.

True

Logical operators can be applied to single bits only.

False

Since process is an infinite loop thus a wait statement at the beginning of a process plays the same role as one located towards its end.

False

A Conditional statement must be terminated by an endif clause.

False

The boolean condition in a while loop is checked at the beginning of each iteration.

True

Execution of a process stops when the end process clause is reached.

False

A process with a sensitivity list may not contain any wait statements.

True

Signals and variables of the same type can be assigned to each other.

True

The expression in the case statement header can be of a discrete type.

True

Process is a specification of sequential operations describing system behavior.

True

The Next statement causes a jump to the next statement after the loop.

False

Process' name is specified after the keyword process.

False

The counter in a for loop is a variable that must be declared at the beginning of a process in which it is used.

False

The Wait statement specifies a condition for suspending the process.

False

Signals are assigned values only when the process suspends.

True

Multiple statements in a then or else clause of a conditional statement must be enclosed within the 'begin … end' delimiters.

False

Both signals and variables can be used to store temporal data inside processes.

False

Only signals can be used as information carriers between processes.

True

Selected signal assignment performs the same action as conditional signal assignment; they are just written in a different way.

False

Stdlogic and stdlogic_vector are industrial standards for logic signals and can be applied to multiple-source signals as well because they are resolved.

True

Each architecture is a set of processes executing concurrently and affecting each other.

True

Processes cannot be used together with concurrent signal assignments in the same architecture.

False

Conditional signal assignment can be used both in architectures (as a concurrent statement) and in processes (as a sequential statement).

False

A signal in a process has only one driver, no matter how many assignments to it the process contains.

True

Processes are so good for specifying systems because the digital world is as sequential as the processes.

False

Bit type as a standard logical type; it does not need a resolution function and can be used for any signals.

False

Each system is typically a set of concurrently working components but at some level its behavior can be specified as a sequence of operations or events.

True

It is possible to specify future events of a signal in one statement.

True

All processes in architecture are active all the time when the architecture is active.

False

Signals on the right hand side of a concurrent signal assignment play the same role as signals on the sensitivity list of a process.

True

A new driver is generated for each declaration of a signal.

False

The if … then … construct can only be used inside processes.

True

Unlike typical statement labels in VHDL, component labels are not optional.

True

Component ports that are not used must be assigned keyword open and cannot be omitted.

False

Using configurations is more flexible and easier than direct instantiations.

False

Components are used directly in the structural descriptions (i.e. are called like subprograms).

False

Architecture name must always be specified in direct component instantiations.

False

Any form of complex signals (single elements', slices or complete signals) can be assigned in port maps.

True

Component declaration reflects the designer needs and not necessarily existing circuit.

True

Structural description consists of components and signals.

True

Configuration specifies the relationship between a component instantiation and its implementation.

True

All components must be specified using behavioral descriptions.

False