Module 3: Sequential Logic Design

Vocabulary practice flashcards covering fundamental sequential logic topics including flip-flops, excitation tables, master-slave circuits, counters, sequence generators, and shift register architectures.

Sequential Logic

Digital logic circuits whose output depends on both currently applied input levels and stored internal binary states (memory).

Combinational Logic

Digital logic circuits whose output depends solely on the current input levels, without any internal memory elements.

Flip-Flop

A two-state, bistable sequential device that serves as a basic $1$-bit memory element designed to change its output at the active edge of a clock signal.

Latch

A bistable sequential device whose output changes are not controlled by a clock edge, responding immediately to level changes on its input lines.

SR Flip-Flop

A one-bit bistable memory device with two inputs: $S$ (SET), which forces the output to $1$, and $R$ (RESET), which forces the output to $0$.

Invalid State (in SR Flip-Flop)

An undefined condition that occurs when both the SET ($S$) and RESET ($R$) inputs are simultaneously set to logic $1$.

D Flip-Flop

A modified Set-Reset flip-flop featuring an inverter between the inputs to ensure that the $S$ and $R$ lines can never simultaneously be at the same logic level.

JK Flip-Flop

A gated modification of the SR flip-flop containing additional circuitry that prevents illegal states by causing the output to toggle when both $J$ and $K$ are logic $1$.

T Flip-Flop

A single-input edge-triggered device constructed by connecting the $J$ and $K$ inputs together, causing the output state to toggle on each active clock pulse when $T = 1$.

Race Around Condition

A problem in a JK flip-flop occurring when $J = K = 1$ and the clock pulse remains high ($\text{CLK} = 1$) for longer than the flip-flop propagation delay, causing the output $Q$ to toggle uncontrollably.

Master-Slave JK Flip-Flop

A configuration of two flip-flops connected in series with complementary clocking via an inverter (master active when clock is high, slave active when clock is low) to eliminate the race around condition.

Excitation Table

A table that lists the present state ($Q_n$) and desired next state ($Q_{n+1}$) on the left to determine the minimum input combinations required on the right to produce that state transition.

Timing Diagram

A diagram used to visualize system interactions along a linear time axis, displaying time on the x-axis and the logic states of interacting signals on the y-axis.

Counter

A sequential logic circuit built from flip-flops and logic gates that cycles through a predetermined sequence of binary states upon receiving clock pulses.

Asynchronous (Ripple) Counter

A counter where flip-flops are not clocked simultaneously; the output of each flip-flop acts as the clock trigger for the succeeding flip-flop, creating cumulative propagation delays.

Synchronous Counter

A counter wherein the clock pulses are applied simultaneously to the clock inputs of all constituent flip-flops, causing state changes to occur concurrently with no ripple delay.

Modulus (MOD-number)

The total number of unique states a counter sequences through during one full counting cycle before recycling back to its starting state, given by $2^n$ for an $n$-bit counter.

Up-Down Counter

A bidirectional counter circuit capable of counting in both increasing (up) and decreasing (down) sequences depending on control inputs.

Ring Counter

A circular shift register counter where the serial output of the final flip-flop is fed directly back into the serial input of the first, recirculating a single preset logic $1$ across $n$ states.

Johnson Counter

A twisted ring counter where the inverted output ($\overline{Q}$) of the final stage is fed back into the input of the first stage, producing a sequence of $2n$ states from $n$ flip-flops.

Sequence Generator

A digital circuit composed of shift registers or counters combined with a next-state combinational decoder designed to generate a prescribed repeating series of bits.

Register

A digital storage unit consisting of a set of $n$ flip-flops used collectively to store and transfer an $n$-bit binary word.

Shift Register

A register capable of transferring or shifting stored binary data internally from one flip-flop to adjacent flip-flops with each applied clock transition.

SISO (Serial Input Serial Output)

A shift register operating mode where data is entered sequentially one bit per clock cycle and retrieved sequentially one bit per clock cycle from the terminal flip-flop.

SIPO (Serial Input Parallel Output)

A shift register operating mode in which binary data is shifted in serially bit by bit, and then read out concurrently across all stages once fully loaded.

PIPO (Parallel Input Parallel Output)

A register operating mode where all input data bits are loaded into the flip-flops simultaneously in one clock pulse and made available simultaneously on the output lines.

PISO (Parallel Input Serial Output)

A register operating mode where bits are loaded simultaneously into flip-flops during load mode (using gating logic) and subsequently shifted out serially one bit per cycle during shift mode.