CSCI 311 exam 2

combinational logic

No loops and output is based on current input, no memory

sequential logic

allows loops, output is based on both the current inputs and past values. Contains loops that create memory

what type of gates do latches use?

NOR gates

what does adding a clock do for a D flip flop?

Helps safeguard timing and creates a d flip flop

what do two d flip flops and an enable pin do?

create the ability to store a single bit of data forever, or until the power turns off

what is an enabled flip flop?

saves the value of D every time the clock changes (mips). this isnt helpful because we want to save only when an enable pin is turned on

Can S and R be set at the same time?

no, simultaneously setting and resetting created garbage output

why does every computer use a clock?

to synchronize all operations

SR latch

takes one bit of memory

built from 2 nor gates

has to inputs

s - set

r - reset

the output is based on both the current input and past values.

state

current values (voltages) of all the inputs, outputs, circuit
nodes, elements, etc.

Race condition

an electronic flaw where a circuit's output depends on the unintended, unpredictable sequence or timing of signals racing through different physical pathways.

In a race condition, what does a propagation delay trigger?

erratic logic states, system glitches, or hardware-level security vulnerabilities.

Asynchronous Circuit

Outputs are fed directly back to inputs, creating race conditions.
A circuit with feedback loops and no clock

Synchronous Sequential Circuit

• To control the current state and make the next state predictable

• registers that are connected to a clock are added to the circuit.

• the clock synchronizes the the data flowing through the circuit.
  A synchronous circuit fixes this by putting registers (flip flops) on a clock in every loop

Four rules for synchronous sequential circuit

1. Every element is a register or a combinational circuit.

2. At least one element is a register.

3. All registers connect to the clock.

4. Every loop contains at least one register.

Finite state machines

• An FSM models a circuit as a set of states (circles) and transitions (arrows).

• The next state depends only on the current state and the current input

• transitions happen on the rising clock edge.

how to read a FSM

1. Start at the arrow labeled “reset” (state A).

2. At each clock edge, find the arrow leaving your current state that matches the input X.

3. Follow it. The output comes from the state label (Moore) or from the arrow (Mealy)

what are the circular loops in a FSM

self- loops they represent a state transition where the system stays in the exact same state when a specific input is recieved

What are the types of FSM used in circuit design?

Moore machine and mealy machine

moore machine

• outputs based only on current state

• outputs associated with states

mealy machine

• outputs based on current state and input

• outputs associated with transitions

• transitions based on next input

purpose of FSM

to control sequential logic, as an FSM remembers past inputs (its current state) to decide what to do next.
to model the behavior of a synchrinous sequanetial diagram

why does it take time for a circuit to settle on an output value?

▪ Not all paths are the same length.
▪ Different types of transistors have different delay times.
▪ Sequential circuits require feedback.

The clock cycle must be long enough for the value to settle.

set up time ★

time the input and clock must be stable before the rising edge

contamination delay ★

minimum time from when the input changes to when the output begins to change

propagation delay ★

maximum time from input change to output has settled on a final value (the slowest path)

clock cycle time ★

• the cycle time of a computer is the time between the rising edges of the clock

• cycle time is measured in hertz

  • megahertz (10^6) hz

  • gigahertz (10^9) hz
    
    

hold time rule

the flip flop must have a hold time less than its contamination delay

propagation delay rules

all elements of the system must have propagation delays less than the clock cycle

clock skew

the clock reaches components at slightly different times, this increases the setup and hold times

synchronizers

external inputs, must pass through a latch to ensure the input is sampled at either high or low (0 or 5 volts)

Maximum clock speed ☆

• Maximum clock speed equals one divided by the minimum cycle time

• Find this cycle time by adding the register output delay, slowest logic propagation delay, and setup time.

throughput ★

amount of work a system can complete in a given time period

parallelism ★

working on multiple calculations at the same time

spatial parallelism ★

multiple copies of hardware

temporal parallelism ★

tasks are broken into parts and completed on an assembly line

FLOPS ☆

floating point operations per second

design levels

• gate levels

• register level

• processor

gate level

process bits, NAND, NOR, flip, flops

register

• process words

• combinational and sequential circuits

processor

• processes block of words

• CPUs, memories, IOPs, etc

word gate

• can perform A OR B where A and B are words

• can perform a bitwise operation on entire binary words rather than a single bit

shift register

A shift register shifts all the bits in word to the left or right, depending on the type of circuit.

For example, passing "01101100" through a Left Shift register
changes the word to "11011000".

multiplexers ★

A mux chooses its single output from multiple inputs based on selection pins.

decoders ★

• A decoder turns on one of several output pins based on the value of the input pins.

• A decoder with N input data pins will turn on one
  of its 2N output pins.

encoder ★

• opposite of a decoder

• 2N input pins and N output pins; only one input is active at a time

PLA (programmable logic arrays)

• is a customizable chip that builds digital circuits using sum-of-products.

• It creates multiplied product terms in an AND section, then adds them together in an OR section for the final output.

the 4 parts of Von Neumann architecture ★

• CPU - ALU for math and logic. CU to direct operations

• memory - contains both instructions and data

• buses - move data between memory, IO, CPU etc

• IO devices

Von Neumann bottle neck ★

The CPU gets all instructions from memory via the bus. The CPU spends a lot of time waiting for memory to read the next instruction, store a new piece of data, etc.

interrupt

• Signal sent by the IO to the CPU to demand attention

  • An I/O device might send an interrupt signal to the operating system when the device has new input data

parity bit

is a single extra bit (a 0 or a 1) at the end of a binary data word to make the total count of 1s an even number.

data register

temporary storage location inside the CPU that holds the actual data currently operated on

address register

stores the specific address location in the memory where a particular instruction or data is residing

program counter

holds the address of the next instruction

instruction register

holds the opcode being decoded

Accumulator

holds the running result

5 ways to measure perfomance

➢ Main Memory Bandwidth - maximum bits per second, in or out
➢ Average Instruction Execution Time
➢ MIPS - Millions of Instructions Per Second
➢ MegaFLOPS - Millions of Floating Point Operations Per Second
➢ Benchmark - program whose main purpose is to exercise the machine

machine code

The zeros and ones that compose an instruction begin with the type of instruction followed by the operands

4 language design requirements

complete, efficient, regular, compatible

completeness ★

1) Data Transfer
- moving data within the CPU and between the CPU and Memory
2) Arithmetic Instructions
- add, subtract, multiply, divide, …
3) Logical Instructions
- Non-numeric operations, such as Boolean operations
4) Program Control
- branching, calling and returning from functions
5) Input-Output

RISC and its 6 componets

Reduced Instruction Set Computer

1) relatively few instructions
2) fixed and easily decoded instruction formats
3) fast instruction execution
4) hardwired control, not microprogramming
5) memory access likely limited to load and store
6) compiler optimizes performance

CISC

Complex Instruction Set Computer

RISC v CISC Comparison ★

RISC
- simple instructions are fast to decode
and execute
- simple instructions don't take up
much memory space
faster retrieval from memory
- more instructions are needed to
execute functions
more memory used
more time wasted waiting on memory

CISC

Much easier for the compiler to
translate your high-level source
code into machine code

varying instruction lengths

____ length instructions save memory space, and short
instruction are retrieved quickly.

Uniform instruction

____ instruction lengths allow easy pre-fetching of
instructions.