Processor Architecture, FDE Cycle, CISC vs RISC, and Pipelining

Flashcards covering CPU components, registers, step-by-step FDE cycle execution, CISC vs RISC comparison, factors affecting CPU speed, and pipelining principles.

What CPU architecture and operational cycle are depicted in this diagram?

The Central Processing Unit (CPU) and Main Memory (RAM) block diagram illustrating the Fetch-Decode-Execute cycle.

What is the primary role of the Control Unit (CU) in a CPU?

The Control Unit controls and coordinates the activities of the processor, fetches instructions from RAM, decodes instructions to determine the required operation, and sends control signals to other components.

What operations are performed by the Arithmetic Logic Unit (ALU)?

The ALU performs arithmetic calculations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT) on data.

What are CPU registers and why are they faster to access than RAM?

Registers are small, high-speed storage locations located inside the CPU that temporarily hold data, instructions, or addresses during processing.

What is the function of the Program Counter (PC)?

The Program Counter stores the memory address of the next instruction to be fetched from memory.

What is the function of the Memory Address Register (MAR)?

The Memory Address Register stores the address of the memory location that is currently being accessed.

What is the function of the Memory Data Register (MDR)?

The Memory Data Register temporarily stores the data or instruction being transferred between the CPU and RAM.

What is the function of the Current Instruction Register (CIR)?

The Current Instruction Register stores the current instruction while it is being decoded and/or executed.

What is the function of the Accumulator (ACC)?

The Accumulator stores intermediate and final results of calculations and logical operations performed by the ALU.

What sequence occurs during steps $1$ through $3$ of the Fetch phase in the FDE cycle?

The address in the Program Counter (PC) is checked, copied into the Memory Address Register (MAR), and then sent along the address bus to RAM, where it waits for a control bus signal.

How is instruction data fetched from RAM into the CIR during the FDE cycle?

The Control Unit sends a read signal along the control bus to RAM, the contents stored at the specified memory address are sent along the data bus to the MDR, and then copied from the MDR into the Current Instruction Register (CIR).

When and why is the Program Counter (PC) incremented during the FDE cycle?

The Program Counter is incremented before proceeding to the decode phase so that the memory address it contains points to the next instruction to be executed.

What are the two components of an $8\text{-bit}$ instruction stored in the CIR?

An OPCODE (which defines what operation to do) and an OPERAND (which defines what to perform the operation on, containing actual data or a memory address).

What steps occur during the Execute phase of a 'LOAD' instruction from memory address $0101$?

The address $0101$ is sent down the address bus to RAM, the Control Unit sends a read signal via the control bus to RAM, the data stored at address $0101$ is sent along the data bus to the MDR, and finally copied from the MDR into the Accumulator.

What are the key characteristics of CISC (Complex Instruction Set Computer) processors?

CISC has a large instruction set containing complex, variable-length instructions that perform multiple operations and take variable clock cycles, requiring complex control circuitry but fewer instructions in a program.

What are the key characteristics of RISC (Reduced Instruction Set Computer) processors?

RISC has a smaller set of simple, usually fixed-length instructions performing a single operation in a predictable number of clock cycles (usually $1$), requiring simpler control circuitry that easily supports pipelining.

How do CISC and RISC compare regarding addressing modes and instruction count per task?

CISC features many addressing modes and requires fewer instructions per program, whereas RISC features fewer addressing modes and requires more instructions per program to complete the same task.

How does the number of CPU cores influence performance?

Having multiple processor cores on a single chip allows more than one instruction to be executed simultaneously.

How do register size and RAM size affect CPU processing?

Register size determines the amount of data the CPU can work with at one time; larger RAM holds more program instructions/data in fast memory, reducing slow data transfers between RAM and the hard disk.

What is clock speed and how is it measured?

Clock speed is the frequency of system clock ticks (turning a transistor off and on) generated by a vibrating quartz crystal, measured in Hertz ($\text{Hz}$); a faster clock executes more instructions per second.

How do data bus width and Cache memory improve CPU speed?

A wider data bus transmits more bits simultaneously, reducing the number of fetches; high-speed Cache directly on the CPU stores recently executed instructions/data (like loops), minimizing memory fetches from RAM.

What is pipelining in CPU processing?

Pipelining is a technique where the CPU overlaps the Fetch-Decode-Execute (FDE) cycle stages of multiple instructions, working on different stages of several instructions simultaneously.

Why is pipelining used, and does it speed up an individual instruction?

Pipelining is used to increase instruction throughput (completing more instructions over time); it does NOT make an individual instruction execute faster.

What is a pipelining hazard?

A pipelining hazard occurs when an instruction depends on the result of a previous instruction before it can execute, causing stalls and preventing pipelining from proceeding normally.