Module I. | VHDL - Terms

VHDL

is a description language for digital electronic circuits that is used in different levels of abstraction.

(Very High-Speed Integrated Circuits) Hardware Description Language

The VHDL acronym stands for VHSIC

VHDL

can be used to accelerate the design process

Hardware Description Language

which allows describing both asynchronous and synchronous circuits.

entity

specifies the input and output ports of the circuit

architecture

describes the behavior of that circuit. An _______ must be associated with an entity

entity

is an abstraction of a circuit, either from a complex electronic system or a single logic gate.

entity

The ports of an _______ can be input(in), outputs(out), input-outputs (inout) or buffer.

Architecture

are used in VHDL to completely describe the operation of a circuit

Architecture

defines how the circuit operates, by including a set of inner signals, functions, procedures, functions

bit

it only admits the values 0 and 1. In order to make an assignment between the object and its value, the latter must be written between single quotes (‘0’ or ‘1’).

bit_vector (range)

always written between brackets, indicates the number of b its of the b—_v——, which is an array of 0’s and 1’s

boolean

it only can take the values true or false.

character

it can take any ASCII characters.

string

any chain consisting of ASCII characters.

integer range

any _______ number within the range, which in this case is not written between brackets. For instance, 0 to MAX. The range is optional.

natural range

Any natural number within the range.

positive range

Any positive number within the range

real range

Any real number within the range

std_logic

Type predefined in the IEEE 1164 standard. This type represents a multivalued logic comprising 9 different possible values.

std_logic_vector (range)

It represents a vector of elements of type std_logic. Its assignment and definition rules are the same ones as the std_logic ones.

VHDL Types

Operators can be used to build a wide variety of expressions that allow to calculate data and/or to assign them to signals or variables

+, -, *, /, mod, rem

Arithmetic operations.

+, -

Sign change

&

Concatenation

and, or, nand, nor, xor

Logical operations

:=

Value assignment to constants and variables

<=

Value assignment to signals

use ieee.std_logic.signed.all;

For vectors that are represented as signed binary:

use ieee.std_logic.1164.all;

use ieee.std_logic.arith.all;

In order to use the pre-defined arithmetic and logic functions

use ieee.std_logic.unsigned.all;

For vectors that are represented as unsigned binary:

Combinational Logic Circuit using VHDL

Combination of different logic gates determined by the logical function of input and output states. Combinational circuits have no memory, timing and feedback loops.

Arithmetic & Logical Function

• Adders

• Subtractors

• Comparators

• PLDs

Data Transmission

• Multiplexers

• Demultiplexers

• Encoders

• Decoders

Code Converters

• Binary

• BCD

• 7-segment

VHDL

It is a language used to: Describe digital circuits, Simulate hardware behavior, Synthesize designs into real hardware (FPGA/ASIC)

VHDL

describes what the hardware does, not step-by-step instructions.

VHDL

• Design large systems efficiently

• Test designs using simulation

• Detect errors before building hardware

• Reuse and modify designs easily

VHDL

commonly used in:

• FPGA design

• ASIC development

• Communication systems

• Automotive electronics

• Aerospace and defense systems

• Industrial controllers

Entity

Defines the inputs and outputs

Architecture

Describes how the circuit works

Signals

Represent wires

Concurrent Execution

Multiple operations happen at the same time

Basic Structure of a VHDL

1. Library declarations

2. Entity declaration

3. Architecture body

VHDL

is based on digital logic concepts such as:

• AND, OR, NOT gates

• Flip-flops

• Counters

• State machines