CEA (copy)

Universal Computation

Concept that any computable problem can be solved by a Turing machine with the correct program.

Programmability

Allows different outputs from the same input by changing the program.

Data Processor

Described as a 'black box' that processes input data based on the program to produce output.

Stored Program Concept

Both data and instructions are stored in memory.

Sequential Execution

Instructions are executed one after another in a sequence.

Memory

Stores data and instructions.

Arithmetic Logic Unit (ALU)

Performs arithmetic and logic operations.

Control Unit

Directs and manages other subsystems.

Input/Output (I/O)

Manages data exchange with external devices.

First Generation Computers

Based on vacuum tubes, large, costly, and unreliable.

Second Generation Computers

Utilized transistors, more reliable, and supported high-level programming languages.

Third Generation Computers

Integrated circuits enabled miniaturization and software packages.

Fourth Generation Computers

Introduction of microprocessors led to personal computers and desktop calculators.

Fifth Generation Computers

Features AI, voice recognition, and natural language processing.

Central Processing Unit (CPU)

Executes instructions and performs calculations, including ALU, control unit, and registers.

Main Memory

Stores data and instructions actively used.

Memory Hierarchy

Registers > Cache > Main Memory > Secondary Storage.

Isolated I/O

Separate address spaces for memory and I/O devices.

Memory-Mapped I/O

Integrates I/O devices into memory space.

CISC

Complex Instruction Set Computer; large instruction set with complex instructions, easier to program.

RISC

Reduced Instruction Set Computer; small instruction set with simple instructions, more efficient.

Pipelining

Executes overlapping instruction stages to increase throughput.

Parallel Processing

Uses multiple processing units to perform tasks simultaneously.

Microprocessor Speed

Increased by pipelining, branch prediction, superscalar execution, data flow analysis, and speculative execution.

Performance Balance

Balancing the performance of different components (CPU, memory, I/O) to avoid bottlenecks.

Multicore

Multiple processor cores on a single chip, enhancing performance through parallelism.

MIC (Many Integrated Cores)

Chips with a large number of cores, posing software challenges to exploit parallelism effectively.

GPU

A specialized core for parallel processing of graphics data.

GPGPU

Using GPUs for non-graphics tasks, leveraging their parallel processing capabilities.

Amdahl's Law

Shows the limit to speedup achievable through parallelization.

Little's Law

Relates the average number of items in a queuing system to arrival rate and time spent in the system.

Clock Speed

Frequency of the system clock, measured in Hertz (Hz).

MIPS

Millions of Instructions Per Second.

MFLOPS

Millions of Floating-Point Operations Per Second.

Arithmetic Mean

Average of all values, useful for execution times.

Harmonic Mean

Useful for comparing rates (e.g., MFLOPS).

Geometric Mean

Appropriate for comparing normalized results (relative performance).

Benchmark Suite

A collection of programs used to evaluate system performance.

SPEC

Standard Performance Evaluation Corporation.

SPEC CPU2017

A widely used benchmark suite for processor-intensive applications.

Von Neumann Architecture

Computer architecture where data and instructions are stored in a single memory space.

Instruction Cycle

The sequence of steps to fetch and execute an instruction.

Fetch Cycle

Retrieving an instruction from memory.

Execute Cycle

Decoding and performing the operation specified by the instruction.

Interrupt

A signal that disrupts normal program execution to handle an event.

DMA (Direct Memory Access)

Allows I/O modules to directly exchange data with memory, improving efficiency.

Shared Communication Pathway

Connection for various components to communicate, typically through a bus.

Bus Interconnection

A shared communication pathway that connects multiple devices.

Control Logic

Handles commands from the I/O module.

Transducer

Converts data between electrical and other energy forms.

Buffer

Temporary data storage.

Programmed I/O

I/O controlled by the CPU.

Interrupt-Driven I/O

I/O relying on interrupts to indicate readiness.

Direct Cache Access (DCA)

I/O modules access cache directly, bypassing main memory.

USB

Widely used external interface for connecting devices.

Interrupt Handler

Routine that handles a specific type of interrupt.

Artificial Intelligence (AI)

A characteristic of fifth-generation computers that perform tasks requiring human-like intelligence.

Cache Memory

Fast memory holding frequently accessed data.

Hit Ratio

Percentage of memory accesses found in cache.

Volatile Memory

Memory that loses its content when power is off.

Non-volatile Memory

Memory that retains its content without power.

Erasable Memory

Memory that can be rewritten.

Error Detection

Identifying errors in memory storage and transfers.

Error-Correcting Codes (ECC)

Detect and correct errors in memory.

Hard Failure

Permanent physical defect in memory.

Soft Error

Random, non-destructive alteration of data.

Microprocessor

An integrated circuit that incorporates the functions of a computer's central processing unit.

SSD (Solid State Drive)

Storage device using semiconductor technology.

HDD (Hard Disk Drive)

Storage device using rotating magnetic platters.

Optical Disk

Storage medium using laser technology to read/write data.

Magnetic Tape

Sequential storage medium using magnetic tape for data.

RAID (Redundant Array of Independent Disks)

Multiple disks configured for performance or redundancy.

RAID 0

Data striped across disks, high performance, no redundancy.

RAID 1

Data mirrored on two disks, high reliability.

RAID 5

Data and parity striped across disks, good performance and redundancy.

RAID 6

Two parity calculations, higher reliability.

Control Unit

Part of the CPU that manages instruction sequencing and execution.

Microprogrammed Control Unit

Control unit that uses microinstructions stored in memory.

Hardwired Control Unit

Control unit built using combinational logic circuits.

Clock Cycle

Basic unit of time for processor operations.

Branch Prediction

Techniques used to guess the outcome of conditional operations to optimize processing.

Pipeline Hazard

Conditions that prevent the next instruction from executing in the next clock cycle.

Data Hazard

A hazard that occurs when instructions depend on the results of prior instructions.

Resource Hazard

Conflicts over hardware resources between competing instructions.

Control Hazard

Allows for predicting the future course of program execution.

Pipelining

An instruction processing technique that allows multiple instruction phases to overlap.

SIMD (Single Instruction, Multiple Data)

Parallel architecture issuing a single instruction to multiple data points.

MIMD (Multiple Instruction, Multiple Data)

Support for executing multiple instructions on different data simultaneously.

NUMA (Non-Uniform Memory Access)

Memory access method where different processors have varying access times.

Chip Multiprocessing (CMP)

Incorporates multiple independent processors onto a single chip.

Thread

The smallest sequence of programmed instructions that can be managed independently.

Vector Processor

A processor designed to handle vector operations.

Control Signal

Signals that determine the control paths in a circuit for executing instruction.

Conditional Execution

Execution of certain statements based on certain conditions.

Superscalar Processor

Processor capable of executing more than one instruction during a clock cycle.

Uniprocessor

A single CPU processing unit.

Micro-operation (μop)

Basic operation executed at the hardware level of the processor.

Data Bus

A pathway used for transferring data between components.

Address Bus

A pathway for transferring addresses between components.

Control Bus

A pathway for transmitting control signals.