PIC24 16-bit MCU Architecture and Programming

Vocabulary practice flashcards covering PIC24 16-bit microcontroller architecture, CPU core features, programmer's model, memory organization, assembly directives, and addressing modes.

Modified Harvard Architecture

A computer architecture implemented in the PIC24 family that features separated memory spaces with a 24-bit wide instruction bus and a 16-bit wide data bus, allowing concurrent access to program and data memory.

Program Counter (PC)

A 23-bit register in the PIC24 CPU core that addresses up to $4\text{M}$ instructions ($4{,}194{,}304$ instructions) in linear program memory, with its least significant bit always fixed at 0.

Single Cycle Instruction Prefetch

The instruction pipeline mechanism in the PIC24 core where an instruction is prefetched concurrently while the current instruction executes, enabling nearly all instructions to execute in a single instruction cycle of 2 clocks.

REPEAT Instruction

An interruptible, overhead-free program loop instruction that repeats the execution of the subsequent instruction for the number of times specified in the RCOUNT register.

PIC24 Hardware Multiplier

A high-speed $17\text{-bit} \times 17\text{-bit}$ hardware multiplier embedded in the ALU that supports signed and unsigned operations, completing all multiplications in a single instruction cycle.

Divide Assist Hardware

Dedicated hardware within the 16-bit ALU that facilitates 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer division operations, completing execution in 18 interruptible instruction cycles.

Working Register Array (W0–W15)

A programmer's model register file consisting of 16 16-bit memory-mapped registers, each capable of serving as a data register, address register, or address offset register.

W15 Register

The working register dedicated to operating as the software Stack Pointer for handling subroutine calls, returns, and interrupt contexts.

SPLIM (Stack Pointer Limit Value Register)

A 16-bit register used to establish the upper memory boundary for the software stack, triggering a stack overflow error trap if W15 exceeds its value.

TBLPAG (Table Memory Page Address Register)

An 8-bit register (bits 0–7) that supplies the upper page address bits when accessing program memory via table read or table write operations.

PSVPAG (Program Space Visibility Page Address Register)

An 8-bit register (bits 0–7) used to select the 32 Kbyte program memory page that is mapped into the upper 32 Kbytes of data space.

RCOUNT (REPEAT Loop Count Register)

A 16-bit register in the programmer's model that holds the iteration count for code execution using the REPEAT instruction.

CORCON (Core Control Register)

A 16-bit CPU control register that contains processor control and configuration bits, including the interrupt priority level bit IPL3 and the Program Space Visibility enable bit (PSV).

STATUS Register (SR)

A 16-bit register split into SRH and SRL containing ALU arithmetic status flags (DC, N, OV, Z, C), the REPEAT loop active bit (RA), and the CPU interrupt priority level status bits (IPL2:IPL0).

DC Bit (ALU Half Carry/Borrow)

Bit 8 of the STATUS register (SR) that is set to 1 if a carry-out occurs from bit 3 during byte-mode operations or from bit 7 during word-mode operations.

RA Bit (REPEAT Loop Active)

Bit 4 of the STATUS register (SR) that indicates loop status; it is set to 1 when a REPEAT loop is in progress and cleared to 0 when it is not.

IPL3 Bit

Bit 3 of the CORCON register indicating if the CPU interrupt priority level is greater than 7; when set to 1, all user interrupts are disabled.

PSV Bit

Bit 2 of the CORCON register that acts as the Program Space Visibility Enable bit; setting it to 1 maps program flash memory into the data memory space.

Phantom Byte

The unimplemented, unallocated high byte (always read as '0') of the upper word in the 32-bit aligned program memory word-pair, occurring because PIC24 instructions are 24 bits wide.

Program Space Visibility (PSV) Area

The upper 32 Kbyte region of the data address space ($8000\text{h} - \text{FFFFh}$, where $\text{EA}\langle 15\rangle = 1$) reserved for accessing read-only constant tables directly from program flash memory.

Near Data Space

The first 8192 bytes of data memory ranging from address $0000\text{h}$ to $1\text{FFFh}$, which can be directly referenced by instructions using memory direct addressing.

Special Function Registers (SFRs)

Core and peripheral control and status registers located in the near data space between memory addresses $0000\text{h}$ and $07\text{FFh}$, typically referenced by symbolic names.

General Purpose Registers (GPRs)

The portion of data memory RAM beginning at address $0800\text{h}$ not reserved for SFRs, allocated for storing dynamic program variables.

Little-Endian Format (PIC24)

The byte-ordering rule wherein multi-byte words are stored in increasing memory addresses with the least significant byte (LSB) at the lower, even address and the most significant byte (MSB) at the higher, odd address.

Register Direct Addressing

An addressing mode in which the instruction explicitly names the working registers containing the source and destination operands (e.g., MOV Wns, Wnd).

Register Indirect Addressing

An addressing mode denoted by brackets (e.g., [Wns]), where the operand value is fetched from or written to the memory address held within the specified working register.

Immediate Addressing

An addressing mode denoted by a '#' prefix indicating that the operand value is a constant literal encoded directly within the instruction rather than a memory address.

lit5

A 5-bit unsigned literal value ranging from 0 to 31 used in PIC24 addition and subtraction instructions to modify working registers with small constants.

.bss Directive

An assembler directive that designates uninitialized variable definitions to be allocated in volatile data memory (RAM), by default starting at address $0800\text{h}$.

.space Directive

An assembler directive used in variable declarations within the .bss section to reserve a specified number of bytes in data RAM.

.text Directive

An assembler directive that marks the beginning of an executable instruction code block targeted for program flash memory.

.equ Directive

An assembler directive used to equate a symbolic constant or label to a fixed numeric value during compilation.

MPLAB C30 Default Integer Sign

The rule in the MPLAB C30 C Compiler where integer types (char, short, int, long, long long) default to signed representation unless explicitly declared with the unsigned qualifier.