ence260 exam (computer architecture and embedded systems)

What is an embedded system

A small computer that has a specific task

Personal computer versus embedded system task type

General task versus specific task

What are the three main components of a computer

Memory and Buses and Central processing unit and Internal peripherals

What is a logic statement

A sentence that answers a yes or no question

What numerical values represent the boolean states FALSE and TRUE

0 and 1 respectively

What does a sequence of logical variables encode

A greater meaning or broader information

What is the formula for the number of possible combinations in a sequence

M to the power of N where M is states per digit and N is sequence length

How many bits are in a byte

8 consecutive bits

What is a word in computer architecture

The default number of bits manipulated by a microcontroller CPU

What is the zeroth bit also referred to as

The least significant bit or LSb

How do you calculate the value of an unsigned binary sequence

The sum of d sub n times 2 to the power of n

What is a shortfall of the sign magnitude representation

It has a duplicate representation for positive and negative zero

Why is twos complement widely used for signed integers

It removes the duplicate zero and lends itself to physical implementation

What are the two steps to convert a positive binary number to a negative twos complement number

Invert each digit and add one ignoring overflow

How many bits are represented by a single hexadecimal digit

Exactly four bits

What is half a byte called

A nibble

What are the three components of a 32 bit floating point binary number

Sign bit and Exponent and Fractional part

How many bits are used in standard ASCII character encoding

7 bits

What type of logic gate output depends only on the current inputs

Combinational logic

What type of logic circuit gives a system memory because output depends on previous states

Sequential logic

What is the simplest form of sequential circuit

The SR latch

What does the introduction of a clock input allow in a D flip flop

The synchronisation of multiple devices to capture and store the input

What is an array of flip flops called

A register

What is a pointer in C programming

A special variable which stores the memory address where the value of the variable is held

What does the asterisk character do to a pointer in C

It gives the value pointed to by the address

What does the ampersand character do to a variable in C

It gives the memory address of the variable

What defines Von Neumann architecture

Programme memory and data memory are stored in the same physical memory space

What defines Harvard architecture

Programme memory and data memory are stored in separate memory spaces

What does the data bus do

Transports actual data between the CPU and memory and is bidirectional

What determines the addressable memory space of an address bus

2 to the power of the bus width

What are the three fundamental logical functions

NOT and AND and OR

What does De Morgans Law state about the inverse of A AND B

It is equal to NOT A OR NOT B

What does De Morgans Law state about the inverse of A OR B

It is equal to NOT A AND NOT B

What is the maximum number of variables a Karnaugh map can analyze

Four Boolean variables

How must adjacent cells in a Karnaugh map differ

By a single variable

What sizes must groups of ones be in a Karnaugh map

Powers of two like 2 or 4 or 8 or 16

What is a minterm

A term written solely as ANDs of all inputs or their inverses where all inputs appear exactly once

What is the standard order of operations for boolean logic

NOT then AND then OR

What is the function of the Arithmetic Logic Unit

It performs arithmetic and comparisons and logic operations

Why are general purpose registers physically close to the ALU

To enable fast access and performance

What does the control and execute unit do

It controls data flow to the ALU and interprets instructions from program memory

What does the Carry flag indicate in the status register

A carry in an arithmetic or logic operation

What does the Zero flag indicate in the status register

A zero result in an arithmetic or logic operation

What does the Negative flag indicate in the status register

A negative result in an arithmetic or logic operation

What does the Program Counter store

The address of the next instruction in the program memory

What does the Stack Pointer store

The address of the top of the stack used for dynamic variable handling

What are the outputs of a half adder

Sum and Carry

How is a full adder created

By cascading two half adders to allow for an incoming carry bit

How does the ALU compare values without dedicated comparison circuits

By using the addition circuit with twos complement subtraction and evaluating the zero and negative flags

Why is twos complement used for signed integers

It eliminates duplicate representations for zero

How do you convert a positive binary number to negative twos complement

Invert each digit and add one

How does the ALU compare values

By adding with twos complement subtraction and checking status flags

What are the outputs of a half adder

Sum and Carry

How is a full adder different from a half adder

It can accept an incoming carry bit

What are the three parts of a 32 bit floating point number

Sign bit and exponent and fractional part

What logic type uses previous states to provide system memory

Sequential logic

What is the simplest sequential circuit

The SR latch

What component is formed by an array of D flip flops

A register

What does the Program Counter store

The address of the next instruction in program memory

What does the Stack Pointer track

The address of the top of the stack

What is the inverse of A AND B according to De Morgans Laws

NOT A OR NOT B

What is the inverse of A OR B according to De Morgans Laws

NOT A AND NOT B

What boolean expression uses solely ANDs of all inputs exactly once

A minterm

How many variables can a Karnaugh map analyze

Up to four Boolean variables

By how many variables must adjacent cells in a Karnaugh map differ

A single variable

What group sizes are allowed in Karnaugh maps

Powers of two like 2 or 4 or 8 or 16

What architecture uses the exact same memory space for programs and data

Von Neumann architecture

What architecture uses completely separate memory spaces for programs and data

Harvard architecture

How is addressable memory space calculated

2 to the power of the bus width

What does an n bit decoder produce

Exactly one HIGH output among 2 to the power n outputs

What does the input of a decoder represent

A binary number selecting one output

What is meant by one hot decoder output

Exactly one output is HIGH at a time

How does a decoder help select memory

It activates the row corresponding to the requested address

What output is HIGH in a 2 bit decoder for input 00

O0

What output is HIGH in a 2 bit decoder for input 01

O1

What output is HIGH in a 2 bit decoder for input 10

O2

What output is HIGH in a 2 bit decoder for input 11

O3

What logic produces O0 in a 2 to 4 decoder

NOT A1 AND NOT A0

What logic produces O1 in a 2 to 4 decoder

NOT A1 AND A0

What logic produces O2 in a 2 to 4 decoder

A1 AND NOT A0

What logic produces O3 in a 2 to 4 decoder

A1 AND A0

What does an encoder do

It converts one active input into its binary input number

What assumption does a basic encoder make

Exactly one input is HIGH

How many outputs does an encoder with 2 to the power n inputs have

n outputs

What does an 8 to 3 encoder output

The 3 bit number identifying the active input

What forms A0 in an 8 to 3 encoder

I1 OR I3 OR I5 OR I7

What forms A1 in an 8 to 3 encoder

I2 OR I3 OR I6 OR I7

What forms A2 in an 8 to 3 encoder

I4 OR I5 OR I6 OR I7

What is the purpose of a multiplexer

Select one of several inputs and connect it to the output

How many inputs can n mux selector bits choose from

2 to the power n inputs

What does a 2 to 1 mux output when S is 0

I0

What does a 2 to 1 mux output when S is 1

I1

What Boolean expression describes a 2 to 1 mux

NOT S AND I0 OR S AND I1

What is a bus multiplexer

Parallel muxes that select between multi bit input buses

What does an 8 by 2 to 1 bus mux contain

Eight parallel 2 to 1 muxes sharing one selector

How can two 2 to 1 muxes form a 4 to 2 bus mux

Use them in parallel with the same selector

What is the purpose of a demultiplexer

Route one input to one selected output

What does a 1 to 2 demux do when S is 0

Routes the input to O0

What does a 1 to 2 demux do when S is 1

Routes the input to O1

What happens to unselected demux outputs

They remain LOW