Digital Logic: Flip-Flop Circuits and Latches

Vocabulary practice flashcards covering logic gate implementations, control inputs, and circuit schematics for SR, JK, T, and D flip-flops.

Clocked SR Flip-Flop

A sequential logic circuit consisting of two input NAND gates controlled by clock ($CLK$), set ($S$), and reset ($R$) inputs, feeding into a cross-coupled NAND gate latch to produce complementary outputs $Q$ and $Q'$.

JK Flip-Flop

A sequential logic circuit having inputs $J$, $K$, and $CLK$, in which feedback lines connect output $Q'$ back to the $J$ input gate and output $Q$ back to the $K$ input gate to eliminate undefined output conditions.

T Flip-Flop

A toggle flip-flop circuit with a common toggle input $T$ and a clock input $CLK$, where input NAND gates receive feedback from outputs $Q$ and $Q'$ and drive a cross-coupled NOR gate latch.

Clocked D Flip-Flop

A sequential circuit with a single data input $D$ and a clock input $CLK$, utilizing an inverter so the lower NAND gate receives the inverted data input ($\overline{D}$) to drive a cross-coupled NAND latch.

Clock Input ($CLK$)

A synchronizing control signal input in clocked sequential circuits that regulates when the flip-flop or latch responds to data and control inputs.

Complementary Outputs ($Q$ and $Q'$)

The dual output terminals of a flip-flop circuit that typically maintain opposite binary logic states, where $Q$ represents the normal stored state and $Q'$ represents its logical inverse.