Computer Architecture and Digital Logic Vocabulary

Vocabulary practice flashcards covering combinational logic circuits, instruction formats, CPU registers, stack operations, interrupts, and memory hierarchy based on the lecture notes.

Decoder

A combinational circuit that converts binary information from input lines into up to $2^n$ unique output lines, where each output represents one minterm.

Encoder

A combinational circuit that performs the reverse operation of a decoder by converting one active input line into a binary code.

Priority Encoder

An encoder circuit that allows multiple inputs to be active simultaneously and produces output corresponding to the highest-priority input line, using a valid output indicator bit $V$.

Multiplexer (MUX)

A combinational circuit that selects binary information from one of $2^n$ input lines and routes it to a single output line using $n$ selection lines.

Read-Only Memory (ROM)

A non-volatile memory device that stores binary information permanently and can implement combinational logic functions using an input decoder and an OR array.

Instruction Code

A group of bits that instructs the computer to perform a specific operation, containing an operation code (Opcode) and an address field.

Operation Code (Opcode)

A group of bits in an instruction code that specifies the particular operation to be executed, such as ADD, SUBTRACT, LOAD, or STORE.

Address Register (AR)

A CPU register that holds the memory address for upcoming read or write operations.

Program Counter (PC)

A CPU register that holds the memory address of the next instruction to be fetched and executed.

Data Register (DR)

A CPU register that holds data read from memory or data waiting to be written to memory.

Accumulator (AC)

A general-purpose register in the CPU that stores operands, intermediate results, and final outputs of arithmetic and logic operations.

Instruction Register (IR)

A CPU register that stores the instruction currently being executed while its contents are decoded by the control unit.

Sequence Counter (SC)

A timing control counter that generates the sequence of timing signals required to order microoperations in the basic computer.

Interrupt

A hardware or software signal that temporarily halts regular program execution to request immediate CPU handling for an event or device.

Interrupt Service Routine (ISR)

A specialized routine executed by the CPU to service a specific interrupt request before resuming execution of the interrupted program.

Control Word

A set of control bits containing SELA, SELB, SELD, and OPR fields that selects source registers, destination register, and the ALU operation in a general register CPU architecture.

Stack

A storage organization structure following a Last In, First Out (LIFO) access sequence, operated using PUSH to insert items and POP to remove items.

Stack Pointer (SP)

A dedicated register that holds the address of the current top element of the stack.

Reverse Polish Notation

A postfix arithmetic notation where operators follow their operands (e.g., $AB+$), eliminating parentheses and allowing efficient evaluation using a stack.

Memory Hierarchy

An arrangement of computer memory levels ordered from fastest and smallest capacity to slowest and largest capacity: Registers $\rightarrow$ Cache $\rightarrow$ Main Memory $\rightarrow$ Auxiliary Memory.

Static RAM (SRAM)

A type of volatile semiconductor memory constructed with flip-flops that retains data without requiring periodic refreshing, commonly used for cache memory.

Dynamic RAM (DRAM)

A type of volatile semiconductor memory that stores data as electrical charge in capacitors, requiring periodic refreshing and providing high density for main memory.

Temporal Locality

The principle stating that memory locations accessed recently by a program are likely to be accessed again in the near future.

Spatial Locality

The principle stating that memory locations physically near recently accessed addresses are likely to be accessed soon.