CS 311 CRUCIAL MUST KNOW THESE!!!!!!!!!!!!!!!!!!!!

You've got this! You may be in a valley, but your MOUNTAINTOP is coming!!!!!!!!!!!!

Design tradeoffs (put this in every answer)

A design tradeoff is a balance among competing goals such as hardware cost, speed, power, instruction size, and ease of programming. Improving one usually hurts another, so there is no perfect design, only tradeoffs.

Von Neumann vs. Harvard

Von Neumann uses one memory for both instructions and data, so it is flexible and used by almost all computers. Harvard uses two separate memories, so each can be optimized, but it is inflexible because the sizes are fixed up front. Tradeoff: flexibility vs. optimization.

The five units of a processor

Controller, ALU, registers (local storage), internal interconnection (data path), and external interface. The controller coordinates everything; the ALU does one operation at a time, only when the controller tells it to. Memory and I/O are outside the processor and connect through the external interface.

Fetch-execute cycle

The processor repeats forever: fetch the next instruction, then execute it. It never stops and only fetches and executes, so software must always give it a next step. An instruction is an opcode (what to do) plus operands (what to do it to).

Fixed vs. variable-length instructions

Fixed-length instructions are all the same size, so hardware can fetch and decode every bit in parallel (hardware is iterated in space). They waste some memory but are much faster. Variable-length instructions save memory but need slower, iterative decoding. Tradeoff: speed vs. memory.

Clock rate vs. instruction rate

The clock is a regular pulse that coordinates the circuits, measured in hertz (cycles per second). A faster clock does not mean one instruction per cycle, because floating point multiply/divide, memory access, and I/O take extra cycles.

ISA and the IBM System/360

An ISA is the instruction set (the operations the hardware understands) plus the instruction representation (their binary format). The System/360 was a family of small, medium, and large computers that shared one ISA, so customers could upgrade without rewriting software. One ISA can have many hardware implementations.

CISC vs. RISC (and MIPS)

CISC has many complex instructions (e.g., Intel x86). RISC has a small set of simple, fixed-size instructions designed so one finishes every clock cycle (e.g., ARM, MIPS). MIPS is RISC because it has a small instruction set (under 50) and simple fixed-size instructions that pipeline well. Tradeoff: RISC has simpler, faster hardware but needs more instructions per program.

The five-stage pipeline

The stages are Fetch, Decode, Execute, Memory, Store (F-D-E-M-S). Each stage works on a different instruction at the same time, like an assembly line. Once the pipeline is full and nothing stalls, one instruction finishes every clock cycle.

Stalls and how to fix them

A stall is when a stage has to wait, usually because an instruction needs a result an earlier one has not produced yet; the gap that moves through the pipeline is a bubble. Causes: data dependencies, branches, subroutine calls, coprocessor use. Fixes: reorder instructions (compiler), insert a NOP (manual fix), or forwarding (hardware fix that passes the ALU result straight to the next instruction).

Registers, register banks, and the Von Neumann bottleneck

Registers are fast memory on the CPU chip, so keep values you will reuse in them. Registers are split into banks so both operands can be read at once; two operands that need different banks but sit in the same one cause a conflict, fixed by an extra copy instruction. The Von Neumann bottleneck: every fetch-execute cycle must read RAM at least once, so memory limits speed. Registers and cache are faster than RAM because they are on the chip, so signals travel a shorter distance.

Branching and condition codes

A branch changes which instruction is fetched next; if/else, loops, and function calls cause them. An absolute branch loads a specific address into the program counter; a relative branch adds an offset to it. To compare two numbers, the ALU subtracts and sets condition codes (positive, negative, zero, overflow), and a conditional branch tests them. Overflow means an error.

Number of operands (0, 1, 2, 3)

The maximum is three, because hardware wants a fixed, small number it can handle all at once. For A = B + C: 0 operands (stack) = push B, push C, add, pop A. 1 operand (accumulator) = load B, add C, store A. 2 operands = move B A, then add C A. 3 operands = add B C A. Tradeoff: more operands means fewer, easier instructions but each is longer; fewer operands means smaller instructions but more of them.

Operand types and cost

An operand can be a register, a memory address, or an immediate value (the data itself, stored in the instruction). An immediate is fast but must be known ahead of time and cannot be a result destination. Cheapest to most expensive: immediate, register, direct memory, indirect, double indirect.

SRAM vs. DRAM

SRAM stores each bit in a latch, so it is fast but uses lots of power and heat. DRAM stores each bit in a capacitor-like circuit (charged = 1), so it uses less power and fits more bits, but the charge leaks and a refresh circuit must constantly rewrite it. Both are volatile. DDR and QDR transfer data at double and quadruple the base rate. Tradeoff: SRAM is faster; DRAM is denser and cheaper, which is why main memory is DRAM.

Memory basics

Memory can only fetch (read) and store (write), and storing overwrites the old value, so nothing is truly deleted. Memory is an array of bytes, and an address is an unsigned integer starting at 0. A 32-bit address reaches 2^32 bytes, which is 4 GB (gigabytes, not gigabits). A pointer is a variable that holds a memory address.