DDCA_Ch4-mine

Chapter 4: Digital Design and Computer Architecture

4.1 Introduction

• HDL (Hardware Description Language): Specifies only the logic function of hardware. It is essential in the design of digital electronic systems.

• Synthesizing Tools: Computer-aided design (CAD) tools convert HDL code into optimized gate-level representations.

• Common HDLs:

  • SystemVerilog:

    • Developed by Gateway Design Automation in 1984; standardized by IEEE (1364) in 1995; extended in 2005 (IEEE STD 1800-2009).

  • VHDL (VHSIC Hardware Description Language):

    • Developed by the Department of Defense in 1981; standardized by IEEE (1076) in 1987; updated in 2008 (IEEE STD 1076-2008).

4.2 Simulation and Synthesis

• Simulation:

  • Inputs are applied to the circuit, and outputs are checked for correctness.

  • Significant cost savings due to debug facilities available in simulation as opposed to hardware testing.

• Synthesis:

  • Transforms HDL code into a netlist, representing the hardware configuration (gates and their connections).

4.3 Module Types in SystemVerilog

• Behavioral Modules: Describes what the module does.

• Structural Modules: Describes how the module is constructed from simpler modules or gates.

4.4 SystemVerilog Syntax

• Case Sensitivity: Identifiers are case sensitive (e.g., reset is different from Reset).

• Naming Rules: Names must not start with numbers, and whitespace is ignored.

• Comments: Can be single-line (// comment) or multi-line (/* comment */).

4.5 Building Modular Designs

• Examples of modules:

  • 3-input AND Gate:

    module and3(input logic a, b, c, output logic y);
      assign y = a & b & c;
    endmodule

  • NAND Gate:

    module nand3(input logic a, b, c, output logic y);
      logic n1;
      and3 andgate(a, b, c, n1);
      inv inverter(n1, y);
    endmodule

• Bitwise Operators: Implement basic logic operations (AND, OR, NOT, etc.) on 4-bit buses.

4.6 Advanced Constructs

• Conditional Assignment Using Ternary Operator:

  • Example of a 2-to-1 MUX:

    module mux2(input logic [3:0] d0, d1, input logic s, output logic [3:0] y);
      assign y = s ? d1 : d0;
    endmodule

• Full Adder Definition: Demonstration of how internal variables are defined and utilized.

4.7 Sequential Logic and Finite State Machines (FSMs)

• Sequential Logic: Uses always_ff constructs for defining clock-based logic.

• State Machine Design:

  module divideby3FSM (input logic clk, input logic reset, output logic q);
    typedef enum logic [1:0] {S0, S1, S2} statetype;
    statetype [1:0] state, nextstate;
    always_ff @(posedge clk, posedge reset)
      if (reset) state <= S0;
      else state <= nextstate;
    endmodule

4.8 Parameterized Modules

• Parameterized Module Example: Allows for flexibility in defining sizes; MUX example with parameterizing width.

  module mux2 #(parameter width = 8) (input logic [width-1:0] d0, d1, input logic s, output logic [width-1:0] y);
    assign y = s ? d1 : d0;
  endmodule

4.9 Testbenches

• Components of a Testbench:

  • Creates clock signals and applies input vectors to the device under test (DUT).

  • Compares expected outputs with actual outputs and outputs errors:

    • Example of a simple testbench:

      module testbench();
        logic a, b, c;
        logic y;
        sillyfunction dut(a, b, c, y);
        initial begin  
          a = 0; b = 0; c = 0; #10;
          // apply more test cases
        end
      endmodule

• Self-Checking Testbench:

  • Automatically verifies output correctness with implemented error checks.

These notes encapsulate significant concepts from Chapter 4, providing a detailed overview of digital design and its associated principles in system architecture.