1.1.1. Structure Function of the Processor

Specification Overview

• 1.1.1 a) Components of the Processor

  • The Arithmetic and Logic Unit (ALU)

  • The Control Unit

  • Registers:

    • Program Counter (PC)

    • Accumulator (ACC)

    • Memory Address Register (MAR)

    • Memory Data Register (MDR)

    • Current Instruction Register (CIR)

  • Buses:

    • Data Bus

    • Address Bus

    • Control Bus

  • Assembly Language Programs

• 1.1.1 b) The Fetch-Decode-Execute Cycle

  • Effect on Registers

• 1.1.1 c) Factors Affecting CPU Performance

  • Clock Speed

  • Number of Cores

  • Cache

• 1.1.1 d) Pipelining in Processors

• 1.1.1 e) Architectures

  • Von Neumann Architecture

  • Harvard Architecture

  • Contemporary Processor Architecture

Components of a Processor

• Functionality: The processor is the "brain" of the computer, executing instructions to allow programs to run.

Arithmetic and Logic Unit (ALU)

• Performs arithmetical (addition, subtraction) and logical operations (AND, OR, NOT, XOR).

Control Unit

• Responsibilities:

  • Directs CPU operations

  • Manages data flow between CPU and devices

  • Accepts, decodes instructions, and stores results.

Registers

• Small, high-speed memory cells for temporary data storage.

• Types of Registers:

  • Program Counter (PC): Address of the next instruction.

  • Accumulator (ACC): Stores results of arithmetic operations.

  • Memory Address Register (MAR): Holds address for read/write operations.

  • Memory Data Register (MDR): Temporarily holds read/write data.

  • Current Instruction Register (CIR): Contains the currently executed instruction, split into operand and opcode.

Buses

• Definition: A set of parallel wires connecting CPU components.

• Types of Buses:

  • Data Bus: Bi-directional, transfers data/instructions.

  • Address Bus: Specifies memory location for operations.

  • Control Bus: Bi-directional, transmits control signals and coordinates bus usage.

• Control Signals Include:

  • Bus request and grant

  • Memory read/write operations

  • Interrupt requests

  • Clock signals for sync.

Assembly Language

• Utilizes mnemonics to represent instructions (e.g., "ADD" for addition).

• Instructions divided into operand (data/address) and opcode (instruction type).

Pipelining

• Definition: Process of executing multiple instructions simultaneously through buffers.

• Types of Pipelining:

  • Instruction Pipelining: Separates the fetch, decode, and execute stages.

  • Arithmetic Pipelining: Breaks arithmetic operations into overlapping stages.

Fetch-Decode-Execute Cycle

• Fetch Phase:

  • PC address stored in MAR

  • Instruction from MAR to MDR via data bus

  • Increment PC

  • Copy MDR to CIR

• Decode Phase:

  • Split contents of CIR into operand and opcode.

• Execute Phase:

  • Executes the decoded instruction.

Factors Affecting CPU Performance

• Key Factors:

  • Clock Speed: Time taken for a clock cycle. Determines how fast operations occur.

  • Number of Cores: Multiple cores can run separate fetch-execute cycles simultaneously, enhancing performance.

  • Cache Memory: Onboard memory for quick access to frequently used instructions.

• Cache Types:

  • Level 1 Cache: Very fast, small capacity (2-64 KB).

  • Level 2 Cache: Medium speed, medium capacity (256 KB-2 MB).

  • Level 3 Cache: Larger, slower memory.

Computer Architecture

Von Neumann Architecture

• Single control unit, ALU, registers, shared memory, and bus for instructions/data.

• Based on the stored program concept.

Harvard Architecture

• Distinct memories for instructions and data, commonly used in embedded systems.

• Optimizes the size of memory cells and their respective buses.

Advantages

• Von Neumann: Cheaper and simpler design.

• Harvard: Faster execution due to parallel fetching of instructions/data.

Contemporary Processor Architecture

• Combines elements of both Harvard and Von Neumann architectures for optimized performance, especially in cache management.