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Introduction to Computer Architecture

• Purpose: Understand the architecture components and their roles in data processing.

• Basics: Includes control unit, arithmetic logic unit (ALU), and register file.

RISC-V Architecture

• 64-bit mode features:

  • 32 integer registers (64-bit each)

  • 32 floating-point registers (64-bit each)

  • Standard register names (e.g., x0 for zero, x1 for return address)

• Registers identified by both index (x0, x1, ...) and ABI names (sp, a0, a1, ...).

Instruction Formats and Classes

1. Types of Instructions:

   • Integer Instructions: Add, subtract, multiply, etc.

   • Logic Instructions: AND, OR, XOR operations.

   • Branch Instructions: beq (branch if equal), bne (branch if not equal).

   • Jump Instructions: jal (jump and link), jalr (jump and link register).

   • Memory Instructions: load and store operations.

   • Floating Point Instructions: Add, subtract, etc. specifically for floating-point numbers.

2. Instruction Formats:

   • Register Type (R-type): Operands are registers.

   • Immediate Type (I-type): One operand is an immediate integer.

   • Store Type (S-type): Store instructions for memory.

   • Branch Type (B-type): For branching.

   • Upper Type (U-type): For setting upper immediate values.

   • Jump Type (J-type): For jump with a larger immediate.

Control Logic in RISC-V

• Instruction pipeline stages:

  1. Instruction fetch (IF)

  2. Instruction decode (ID)

  3. Execute (EXE)

  4. Memory access (MEM)

  5. Write back (WB)

Application Binary Interface (ABI)

• Defines how registers are used for standard interoperability between code.

• Each register has a designated purpose (argument registers, saved registers, etc.).

• Example register usage for functions:

  • a0-a7 for arguments

  • s0-s11 for saved values

• ABI helps manage memory layout for arguments and function calls.

Memory Structures in RISC-V

1. Executable Sections:

   • .text: Code section (CPU instructions)

   • .data: Initialized global variables.

   • .bss: Uninitialized global variables.

   • .rodata: Read-only data.

2. Stack Memory Management:

   • Stack grows downwards from high to low memory.

   • Stack pointer must be aligned to 16 bytes.

   • Frame pointers mark the base of function stack frames.

Data Types and Endianness

• Endianness determines storage and access format of multi-byte data:

  • Little Endian: LSB first (common in RISC-V).

  • Big Endian: MSB first.

• Impacts how data is stored and accessed between architectures.

Floating-Point Representation (IEEE-754)

• Defines binary representation of floating-point numbers, including sign, exponent, and fraction.

• Example Conversion:

  1. Determine sign bit (0 for positive, 1 for negative).

  2. Use an exponent with a bias for representation.

  3. Handle normalization to fit format requirements.

Arithmetic Operations

• In binary: addition, subtraction, multiplication, and division.

• Use of two's complement for negative numbers.

• Focus on efficient algorithms for bitwise operations integrating carry and overflow checks.

Pseudo Instructions in Assembly

• Simplifies certain complex assembly tasks into manageable commands for programmers.

• Common examples include jumps and store functions that leverage hardware capabilities.

• Importance of understanding ABI around pseudo-instructions for effective assembly coding.

Conclusion

• Understanding computer architecture is crucial for creating efficient programs and utilizing the underlying hardware effectively. RISC-V's design facilitates simple and efficient operations while adhering to a logical instruction set.