CENG335_Lecture1_Introduction_to_CAD_and_VHDL
CENG335: Digital Logic II
Lecture 1: Introduction to CAD tools and VHDL
Instructor: Dr. Hussein Kobeissi
Outline
Introduction
Introduction to CAD tools
CAD tools
Introduction to VHDL
VHDL: Digital signal, Entity and Architecture
Example and Exercise
Introduction
Historical context: Early digital circuits were designed with vacuum tubes and transistors.
Introduction of Integrated Circuits (IC): Combination of multiple logic gates on a single chip.
Evolution: Early ICs had a limited number of gates, but advancements allowed for hundreds/thousands on one chip.
Automation necessity: As circuit complexity grew, automating design processes became essential.
Verification issue: Traditional breadboards were insufficient for complex circuit validation.
Emergence of Computer-aided tools became critical for design.
Introduction to CAD Tools
Manual Design Limitation: Small circuits may be manually designed (as learned in Digital Logic 1), but larger logic systems require automation.
CAD: Abbreviation of Computer Aided Design, which provides tools for complex circuit design.
Types of CAD Tools Needed
A comprehensive CAD system includes tools for:
Design Entry
Synthesis and Optimization
Simulation
Physical Design
CAD Tools – Design Entry
Design Process:
Conduct initial manual design planning: envisioning circuit functionality and structure.
Importance of design experience and intuition at this stage.
Methods:
Schematic Capture
Writing in Hardware Description Languages (HDL)
CAD Tools – Design Entry: Schematic
Definition: Graphical representation of circuit elements (logic gates) with interconnecting wires.
Functionality:
Uses graphics/libraries for circuit diagram drawing.
Hierarchical design is feasible (sub-circuits can be reused).
Advantages/Disadvantages: Simple for smaller circuits, but inefficient for large designs.
CAD Tools – Design Entry: HDL
HDL: Represents hardware through a programming language structure.
Prominent HDLs:
VHDL (Very High Speed Integrated Hardware Descriptive Language)
Verilog HDL
Logic Representation: In HDL, signals are modeled as variables and logic functions assigned values based on these variables.
CAD Tools – Synthesis
Synthesis Process: Converts initial specifications into a functional logic circuit.
Input/Output:
Input: Schematics or HDL code.
Output: Logic gate expressions describing the circuit.
Optimization: Synthesis tools enhance circuit designs, especially for large circuits.
CAD Tools – Functional Simulation
Simulates the generated logic expressions to verify expected behavior.
Utilizes a functional simulator to evaluate output based on inputs provided by the designer.
Results visualization through synchronous timing diagrams.
CAD Tools – Physical Design
Transition from logical expressions to physical implementation on a chip.
Mapping: Determines placement for logic elements and wiring utilized in chip design.
CAD Tools – Timing Simulation
Propagation Delay: Evaluates signal output time delays in logic elements.
Consists of delays from logic elements and signal propagation through connecting wires.
Timing Evaluation: A timing simulator assesses whether design meets timing specifications. Adjustments may be needed if requirements are unmet.
CAD Tools – Chip Configuration
Chip Programming: Final step in the design cycle, ensuring compliance with specifications.
Steps in chip programming include
Validation of design requirements.
Connection to an FPGA chip.
Programming the chip.
Introduction to VHDL
Development of HDLs was driven by the need to describe complex digital circuits.
VHDL Standards:
Original: IEEE 1076 (1987)
Revised: IEEE 1164 (1993)
Updates: 2000 and 2002.
VHDL usage: Focuses on designing hardware rather than sequential programming, with a potential for simultaneous execution of code lines.
VHDL – Why it is Important?
VHDL allows system behavior modeling and pre-synthesis verification, a necessity for designers.
Comparatively easier than Verilog, especially for those familiar with programming languages like C++ or Python.
Supported widely across:
Digital hardware organizations
Online forums
Design Portability: Circuits designed in VHDL can be implemented across various chips and CAD tools without code alterations.
VHDL – Digital Signal Representation
VHDL consists of two core parts:
Entity: Defines the input/output signals, describing the circuit's external interface.
Architecture: Details the internal functionality of the circuit.
Data Objects: Logic signals represented as data objects; includes standard types like BIT (0/1).
VHDL – Writing a Code Example
Logic Circuit Definition:
Declare input/output signals using the Entity construct.
Define circuit functionality with the Architecture construct.
VHDL – Example Continued
Entity Naming: Must have a unique name (e.g., "example1").
Port definitions: Each port associated with input (IN) or output (OUT) mode needs correct naming conventions:
Valid characters include letters, numbers, and underscores.
Name should not be a VHDL keyword.
VHDL – Example Continued
Architecture Naming: Assign a descriptive name (e.g., "LogicFunc").
Built-in Boolean Operators: Supported operators include AND, OR, NOT, NAND, NOR, XOR, and XNOR.
Structure Requirements: Each architecture must include a START and END keyword and relate back to the entity.
VHDL – Complete Example Code
ENTITY example1 IS
PORT (x1, x2, x3 : IN BIT; f : OUT BIT);
END example1;
ARCHITECTURE LogicFunc OF example1 IS
BEGIN
f <= (x1 AND x2) OR (NOT x2 AND x3);
END LogicFunc;VHDL – Exercise: Circuit Construction
Given the following VHDL code, draw the corresponding circuit:
ENTITY example2 IS
PORT (x1, x2, x3, x4 : IN BIT; f, g : OUT BIT);
END example2;
ARCHITECTURE LogicFunc OF example2 IS
BEGIN
f <= (x1 AND x3) OR (x2 AND x4);
g <= (x1 OR NOT x3) AND (NOT x2 OR x4);
END LogicFunc;