Additional Notes 1: Phase Locked Loop Fundamentals

PHASE LOCKED LOOP (P.L.L.) FUNDAMENTALS

• The general block diagram of a Phase Locked Loop (P.L.L.) includes several subsystems:

  • Phase Detector (PD): Outputs a voltage proportional to the phase difference between the input and the V.C.O.

  • Equation: Vd = KD (\theta{in} - \theta{out})

  • Loop Filter (LF): Smooths the output of the PD to control the V.C.O.

  • Function: Filters the error signal to produce a control voltage.

  • Voltage Controlled Oscillator (V.C.O.): Generates a signal whose frequency is controlled by an input voltage.

  • Output: V{out} = A \cos(\omega{o} t + \phi)

  • Frequency Divider (÷ N): Reduces the frequency of the oscillator output for synchronization purposes.

PHASE DETECTOR EQUATIONS

• The output voltage of the phase detector is defined by:

  • Output: Vd = KD \cdot e

  • Where: K_D = [V/rad]

  • Input signals can be represented as:

    • V1(t) = A \sin(\omega1 t + \phi_1)

    • V2(t) = B \cos(\omega0 t + \phi_0)

LOOP FILTER

• The Loop Filter stabilizes the response of the P.L.L.

  • Passive Loop Filter:

  • Transfer Function: F_1(S) = \frac{1}{\tau + 1}

  • Active Loop Filter:

  • More complex with multiple poles and zeros designed to optimize bandwidth and stability.

VOLTAGE CONTROLLED OSCILLATOR (V.C.O.)

• The frequency response of a V.C.O. is defined by:

  • f{VCO} = \text{Control Voltage} \cdot K0

  • Deviation from center frequency: \Delta \omega = K0 \cdot Ve \cdot \frac{dV_e}{dt}

LOOP EQUATIONS

• The relationship between input voltage and output can be modeled in the Laplace domain as:

  • V1(s) = KO rac{KD}{N} F(s) imes Ve(s)

  • Closed-loop transfer function can be represented as:

  • H(s) = \frac{K{O} K{D} / N imes F(s)}{s + KO KD / N imes F(s)}

• Where:

  • K' = KO KD / N

  • H(s) is fundamental to understanding stability and response in feedback systems.

DIVIDER

• Divides the output of the V.C.O. by integer values of N, allowing access to a range of clock frequencies:

  • \theta(t) = A \cos(\omega_0 t + \phi)

NOISE PERFORMANCE

• The P.L.L. operates as a narrowband filter, improving selectivity and noise rejection:

  • Loop noise bandwidth, B_L = \sqrt{\int |H(j\omega)|^2 d\omega}

LOCKING PERFORMANCE

• Conditions for locking depend on input signal frequencies and loop bandwidth:

  • Locking occurs when input phase/frequency is within loop filter bandwidth.

  • Pull-in frequency difference: \Delta \omega{max} = \frac{K'}{25 \omegan}

ACQUISITION TIME

• Time to achieve synchronization is a function of various parameters:

  • Average acquisition time, TA = \frac{1.3}{BL}

  • Factors affecting this include the initial frequency offset.

SYNCHRONIZER EXAMPLE

• A practical example includes designing a synchronizer that can acquire signals within a defined number of symbol periods.

  • Loop parameters are critical, e.g., damping factor, mean acquisition time, and loop division factor must be calculated correctly.

• Loop Bandwidth adjustments are crucial for both initial acquisition and synchronization stability:

  • Bandwidth should be broader during acquisition and tapered down for stable operation.

SYNTHESIS OF LOOP PARAMETERS

• Selecting external components like resistors and capacitors effectively tunes the loop filter for desired performance:

  • Utilize manufacturer curves and specifications for components to determine suitable values.

  • Commonly involves a combination of timing circuits and logic gates for digital implementations.

REFERENCE MATERIALS

• Key texts for further study include:

  1. K. Feher - Digital Communications: Microwave Applications

  2. WR Bennett, Jr. - Data Transmission

  3. WC Lindsey and M. K. Simon - Telecommunication Systems Engineering

  4. FM Gardner - Phaselock Techniques

  5. A. Viterbi - Principles of Coherent Communication