Computer Architecture and CPU Fundamentals

CPU Basics

  • What does CPU stand for?

    • Central Processing Unit

  • What does PC (Program Counter) store?

    • The next instruction’s address

  • What does IR (Instruction Register) store?

    • The current fetched instruction

  • What does MAR (Memory Address Register) store?

    • The memory address to access

  • What does MBR (Memory Buffer Register) store?

    • Also called MDR (Memory Data Register), it stores the data/instruction being transferred to/from memory.

  • Which component performs arithmetic and logic operations?

    • ALU (Arithmetic Logic Unit)

  • In the Fetch step, the CPU usually:

    • Copies the instruction into IR and increments PC.

  • Correct order of the main instruction cycle:

    • Fetch → Decode → Execute

  • ICC (Instruction Cycle Code) is used to indicate which cycle stage the CPU is in. Which ICC value means Execute?

    • 10

  • General Register-based CPU Organization:

    • This type of organization uses two or three address fields in their instruction format.

  • IR (Instruction Register) holds the address of the next instruction to fetch.

    • False

  • MAR (Memory Address Register) answers “WHERE in memory?”

    • True

  • MBR/MDR (Memory Buffer/Data Register) answers “WHAT data is being transferred?”

    • True

  • PC (Program Counter) usually increases after fetch to point to the next instruction.

    • True

  • Four main CPU registers used in the instruction cycle:

    1. PC - Program Counter

    2. IR - Instruction Register

    3. MAR - Memory Address Register

    4. MBR/MDR - Memory Buffer Register / Memory Data Register

  • Three main steps of the instruction cycle in correct order:

    1. Fetch

    2. Decode

    3. Execute

  • Four ICC (Instruction Cycle Code) states and meanings:

    1. 00 - Fetch Cycle

    2. 01 - Indirect Cycle

    3. 10 - Execute Cycle

    4. 11 - Interrupt Cycle

  • Two main stack actions and their functions:

    • Push: adds data to the top of the stack

    • Pop: removes data from the top of the stack

  • Types of instruction formats based on the number of addresses:

    • Zero-address instructions

    • One-address instructions

    • Two-address instructions

    • Three-address instructions

  • Three CPU organization types:

    • General Register-based CPU Organization

    • Single Accumulator-based CPU Organization

    • Stack-based CPU Organization

Addressing Modes

  • Base register addressing mode is used to implement inter-segment transfer of control. Addressing mode:

    • Base Register Addressing Mode

  • Register Indirect Mode:

    • In this addressing, the operand’s offset is placed in any one of the registers: BX, BP, SI, DI as specified in the instruction.

  • Instruction to call a subroutine:

    • Call

  • Instruction to skip over rungs in PLC (Programmable Logic Control):

    • Jump

  • Hypothetical computer designed by Leland Beck to demonstrate the fundamental inner workings of a computer:

    • Simplified Instructional Computer (SIC)

  • Method dividing complex problems into smaller tasks executed simultaneously:

    • Parallel Computing

  • Any goal-oriented activity requiring, benefiting from, or creating computers:

    • Computing

  • Multiple separate computers connected over a network working together on a single goal:

    • Distributed Computing

  • Named after Gene Amdahl for the bottleneck effect on performance:

    • Amdahl’s Law

  • First model of computing (1940s):

    • Sequential Computing

    • Operates like a single-file line, with one task finishing before the next starts.

  • Bottleneck processing time example:

    • If a system has a single bottleneck occupying 20% of total execution time, with 4 additional processors, the speedup would be calculated as follows:

    • P = 20 ext{%}, N=5N = 5

    • Speedup ≈ 1.19

  • Finding Overall Speedup from enhanced tasks:

    • Fraction Enhanced: 60%

    • Speedup Enhanced: 4

    • Overall Speedup ≈ 1.818

Control Units

  • Main function of the Control Unit (CU):

    • Direct and coordinate operations of the CPU.

  • Component used by Control Unit to determine operation:

    • Instruction register.

  • Key characteristic of a Hardwired Control Unit:

    • Generates control signals using fixed hardware circuits.

  • In microprogrammed control unit with single-level control store:

    • The opcode of an instruction provides the address of the microprogram in control memory.

  • Main advantage of a two-level control store:

    • Reduces memory size by avoiding repeated control signals.

  • Function of the Control Unit in a CPU:

    • Direct the flow of data and generate control signals.

  • Characteristic of a Hardwired Control Unit:

    • Generates control signals using fixed logic circuits.

  • Why is a Micro-programmed Control Unit generally slower?

    • It requires fetching microinstructions from control memory.

  • What is a Control Word in microprogramming?

    • A binary word where each bit represents a control signal.

  • Major difference between Horizontal and Vertical Micro-programmed Control Units:

    • Horizontal represents each control signal with one bit.

  • Synchronous data transfer uses:

    • A common clock signal to control communication.

  • Factors affecting data rate in synchronous data transfer:

    • Clock frequency and bits per clock cycle.

  • Disadvantage of synchronous data transfer:

    • A slow device can reduce the overall system speed.

  • Asynchronous data transfer uses:

    • Start and stop bits to indicate the beginning and end of data.

  • Flexibility of Asynchronous data transfer:

    • Devices can operate at different speeds.

  • In horizontal micro-programmed control units, control signals are:

    • Decoded and directly represented in the control word.

  • TRUE statement about vertical micro-programmed control units:

    • Control signals are encoded and require decoding.

  • Control word size in horizontal programming for 64 control signals and 16 flags:

    • Total Control Word Size = 80 bits

  • Vertical micro-programming requirement for 64 control signals:

    • Requires 6 bits.

  • Comparison of horizontal to vertical micro-programming:

    • Horizontal micro-programming is generally faster and more flexible.

Pipelining and Performance

  • Primary function of pipelining in a CPU:

    • Allow for the simultaneous execution of more than one instruction.

  • Three primary ways to measure the performance of a computer:

    • Response Time

    • Throughput

    • CPU Execution Time

  • Classifications of microprocessors:

    • RISC

    • CISC

    • EPIC

  • What do we call the small basic actions performed inside the CPU?

    • Micro-operations

  • Primary determinant of how quickly a computer executes instructions:

    • Processor Speed (measured in GHz).

  • Stage that retrieves the instruction from memory:

    • Fetch.

  • Complete process of Fetch, Decode, Execute, and Interrupt called:

    • Instruction Cycle.

  • Three types of data hazards:

    • RAW (Read After Write)

    • WAR (Write After Read)

    • WAW (Write After Write)

  • Pipeline type where all stages take the same time to complete an operation:

    • Uniform Delay Pipeline.

  • Amount of work accomplished by a computer system:

    • Computer Performance.

  • Processing unit on a single chip:

    • Microprocessor.

  • Dependency arising from resource conflict in the pipeline:

    • Structural Dependency.

  • RISC processor has:

    • 5 stage instruction pipeline to execute all the instructions.

  • Cycle in the pipeline without new input:

    • Stall.

  • Micro-operation that moves data from a register back to memory:

    • Store.