Lecture Simple CPU Part 2: Basic Processing Unit Fetch

Lecture Simple CPU Part 2: Basic Processing Unit Fetch

Overview

  • Lecture Reference: Hamacher, Chapters 5 and 7.1-7.2

  • Copyright Information: © Jan 2026, Donald Davis and T. Obuchowicz. All rights reserved. No use permitted without prior consent.

Basic Processor

  • Definition: The central processing unit (CPU) serves as the control center of a computer, overseeing operations including data transfer and manipulation.

  • Components:

    • Registers: Internal data storage mechanisms whose size and number depend on the system architecture.

    • Arithmetic Logic Unit (ALU): Component responsible for data manipulation.

    • Control Unit: Manages instruction decoding, control line activation, and operation timing.

    • Bus: A series of transmission lines that connect various components for data transfer.

    • Memory Address Register (MAR) & Memory Data Register (MDR): Dedicated registers with their own buses, facilitating access to main memory while the bus is active

Basic Processor: Fetch

  • Instruction Fetching:

    • The CPU typically fetches instructions from the main memory.

    • The current value of the program counter (PC) directs the fetch request to a specific memory address.

    • The contents located at this memory address are loaded into the instruction register (IR).

    • The PC is then updated to point to the address of the subsequent instruction.

    • Contents of the IR are decoded into operational instructions, which include the OP code, source, and destination (refer to Textbook Appendix C tables C.1, C.3, C.4, C.5, and C.6).

Instruction Format Example for 68000 CPU

  • Instruction Structure: The 68000 architecture utilizes a 16-bit word for instructions, requiring an arrangement of bits for various operations:

    • Up to 6 bits determine the source and destination of the operation.

    • The remaining bits are used for the OP code.

  • Example of MOVE Instruction Coding: 00SS RRRM MMee eeee

    • Legend:

    • S = Size of data to be moved (byte, word, long word)

    • R = Destination register number

    • M = Effective address mode of the destination

    • e = Additional bits to define the effective address mode and register number of the source data.

  • Memory Access Requirement: Some instructions may necessitate additional memory access to load data from a specific memory location to a register or to store immediate data into memory.

Fetching Process Steps

  1. Loading Instruction:

    • The fetch process begins by loading the instruction. The contents of the PC are transferred to the MAR via the bus.

    • The PC is incremented, and its new value is loaded into the results register of the ALU during the same cycle.

  2. Memory Access:

    • The contents of the memory addressed by the MAR are loaded into the MDR. Simultaneously, the incremented value from the results register is assigned back to the PC.

  3. Loading IR:

    • The contents of the MDR are then transferred to the IR using the bus.

    • If the instruction is single-cycle, the execution portion will commence immediately. Otherwise, further memory access may be required.

Basic Processor: Execute

  • Execution Process: If additional memory access is necessary, the instruction carries source and destination address information.

  • Decoding:

    • The source address is decoded and loaded onto the MAR through the bus.

  • Loading Data:

    • The contents corresponding to the MAR address are accessed and loaded into the MDR.

    • The MDR contents are subsequently directed to the designated location using the bus. This process can be repeated as needed.

  • Example Operation: For an operation such as SUB <LOC1>, D2:

    1. Load the address of <LOC1> into the MAR.

    2. Load the contents of the MAR into the MDR.

    3. Load the contents of register D2 into the ALU's temporary register.

    4. Feed the MDR contents to the ALU and store the results in the ALU's results register.

    5. Finally, load the contents of the results register into register D2 via the bus.

Memory Access Timing

  • Access Times:

    • Accessing main memory is generally slower than accessing registers.

    • To manage this, an additional control signal known as the Memory Function Complete (MFC) is employed. Once memory access is finished, the MFC signal goes high, indicating the processor can proceed to the next cycle (for instance, moving data from the bus to another location).

    • The MFC can be activated by a stable voltage level on the bus lines from register circuitry.

Basic Processor: Branch

  • Branch Instructions: This type of instruction provides an offset to the PC, allowing for the next instruction to be fetched from a non-sequential memory address.

  • Execution of Branch:

    • Upon encountering a branch instruction, the PC is first incremented.

    • The branch instruction is then loaded into the IR.

    • The instruction contains displacement information indicating the value to be added or subtracted from the current PC value.

    • The updated PC value is already present in a temporary register (from the previous increment), and the displacement is input into the other ALU input. The resultant value is loaded back into the PC during the subsequent clock cycle.

    • The PC is loaded into the MAR, the contents of the MAR are loaded into the MDR, and finally, the MDR contents are loaded into the IR.

    • Note the distinction: while MAR and MDR possess their own buses, other operations utilize the memory bus and may require multiple cycles for completion.

Basic Processor: Conditional Branch

  • Conditional Branching: In the case of conditional branch instructions, the offset is loaded only if the looping condition meets certain criteria, specifically dictated by the status register values.

  • Fallback Handling: If the condition fails, the unmodified PC value is directly loaded into the MAR, directing the CPU to continue executing sequentially.

Multiple Bus Processor

  • Optimization via Multiple Buses: To enhance the processor's performance by minimizing instruction cycle counts, a multiple bus architecture allows for the simultaneous transfer of contents from more than one register.

    • Design Features:

    • Components are optimized for this configuration through multiple input connections and a streamlined structure (a singular general-purpose register array).

    • Dedicated circuits for tasks like PC incrementing, which don't use the bus, thereby freeing up resources for other operations, contribute to the increase in system speed compared to traditional single-bus designs.

Next Lecture

  • Preview: The discussion on basic processors will continue in the next lecture.