3---Sequential-Logic-Design_2022_Digital-Design-and-Computer-Architecture

Sequential Logic Design

3.1 Introduction

• Purpose of Sequential Logic: To analyze and design circuits where outputs depend on current and prior input values; sequential logic has memory.

• State Variables: A set of bits called state variables contains all past information needed to describe future behavior.

• The usage of Synchronous Sequential Circuits: Built using combinational logic and flip-flops to contain state information.

3.2 Latches and Flip-Flops

3.2.1 Bistable Elements

• Bistable Element: A circuit capable of maintaining one of two stable states (0 or 1).

• Cross-Coupled Inverters: Form the simplest bistable element; outputs Q and Q' depend cyclically on each other.

  • Metastable State: A state where both outputs are approximately halfway between 0 and 1; needs to avoid in practical designs.

3.2.2 SR Latch

• Comprised of two cross-coupled NOR gates.

• Inputs: Set (S) and Reset (R); they control the output (Q) state.

  • Truth Table includes four cases depending on the state of S and R.

• Outputs: Q maintains its old state when S and R are both 0.

3.2.3 D Latch

• Functionality: Distinguishes between what the next state should be (input D) and when it will change (CLK).

• Truth table behavior is similar to SR latch but avoids problems with simultaneous assertions of S and R.

  • Transparent Latch: When CLK = 1, data at D flows to Q.

3.2.4 D Flip-Flop

• Composed of two D latches controlled by complementary clock signals.

• Functionality: Copies D to Q on the rising edge of CLK; retains state at all other times.

  • Edge-Triggered: Changes state only on clock edges, enhancing reliability.

3.2.5 Registers

• A collection of flip-flops (N-bit register); all share a common clock signal and are updated simultaneously.

3.2.6 Enabled and Resettable Flip-Flops

• Enabled Flip-Flop: Has an additional input (EN) that controls whether data is loaded on the clock edge.

• Resettable Flip-Flop: Can preset the output based on a RESET signal, either synchronously or asynchronously.

3.2.7 Transistor-Level Designs

• Discusses the implementation of latches and flip-flops in CMOS technology.

3.3 Synchronous Logic Design

• Sequential circuits characterized as those with cyclic paths; cyclical paths lead to challenges like race conditions.

• Synchronous Circuits: Include registers and combinational logic that are synchronized by a clock signal, preventing race issues.

• Timing specifications must be observed, including setup time, hold time, and propagation delays, which affect the overall design.

3.4 Finite State Machines (FSMs)

• Definition: Composed of a number of states and transitions based on input; essential for controlling sequences.

• Moore and Mealy Machines: Differentiated by output dependencies on states vs. current inputs.

• Design Process: Identify inputs/outputs, sketch state transition diagrams, create state transition tables, and derive Boolean equations for transitions and outputs.

• Encodings: Choosing effective binary or one-hot encodings for state representation is crucial.

3.5 Timing of Sequential Logic

• Setup and Hold Times: Critical for ensuring stable inputs during clock transitions to prevent metastability.

• Clock Skew: Timing variation can impact performance; need mechanisms to ensure reliable state sampling against setup/hold time violations.

3.6 Parallelism

• Latency: Time taken for a token to traverse through the system.

• Throughput: Volume of tokens processed per unit time; can be improved via spatial or temporal parallelism.

• Pipelining: A form of temporal parallelism that enhances throughput while managing task dependencies.

3.7 Summary

• Sequential Logic: Outputs depend on inputs and historical data; flip-flops are the building blocks for storing state.

• Design Techniques: Systematically apply FSM principles to design reliable digital systems, focusing on timing constraints and state management.