Overview: The fetch-decode-execute cycle is fundamental to the operation of a CPU, allowing it to process instructions. It consists of several stages that allow the CPU to execute programs.
Increment the Program Counter (PC): The address held in the Program Counter is copied to the Memory Address Register (MAR) to fetch the instruction.
Fetch the Instruction: The instruction is retrieved from memory and placed in the Memory Data Register (MDR).
Copy the Instruction: The instruction is then moved from the MDR to the Current Instruction Register (CIR).
Decode the Instruction: The CPU decodes the instruction to understand what action is required.
Execute the Instruction: The CPU executes the instruction as decoded.
Update the PC: The PC is incremented to point to the next instruction in sequence.
Cycle Repeats: The cycle then continues with these steps as new instructions are fetched.
Moore's Law: Proposed by Gordon Moore in 1965, suggests that the number of transistors in a processor doubles every two years, leading to better performance.
Benefits of More Transistors: Increased transistor count allows more complex processing capabilities such as better ALUs (Arithmetic Logic Units), larger registers, and more memory addresses available for RAM.
Function: The clock sends a timing signal to the Control Unit, measured in Hertz (Hz).
Effect: A higher clock speed enables more operations per second, enhancing performance.
Some operations take longer to complete, and data travel time over buses must be considered.
Factors like power consumption and heat generation also limit performance.
Refers to a smaller, faster memory located within the CPU that stores frequently accessed data and instructions.
Speeds up access times compared to standard RAM by preloading sequential memory addresses.
Cores: More cores on a CPU allow parallel processing, sustaining or increasing performance without boosting clock speeds.
Limitations of Cores: Not all programs can effectively utilize multiple cores; management of processes can introduce delays and data transfer bottlenecks.
Transistors on chips are measured in nanometers (nm); smaller sizes generally lead to better performance.
Innovations have led to increases in transistor capacity, such as IBM's 2nm process accommodating up to 50 billion transistors in a chip the size of a fingernail.