Overview

• Focus: Methodology

• Architecture: Combinational Logic Circuits

• Textbook References:

  • v4: Ch3 3.1, 3.2, 3.3

  • v5: Ch3 3.1, 3.2

• Core Ideas:

  1. BCD-to-Seven-Segment Decoder

  2. 4-Bit Equity Comparator

  3. Technology Mapping

Systematic Design Procedures

1. Specification: Write a specification for the circuit.

2. Formulation: Derive relationship between inputs and outputs using truth tables or Boolean expressions.

3. Optimisation: Apply optimisation to minimise the number of logic gates and literals required.

4. Technology Mapping: Convert design to a new diagram using available implementation technology.

5. Verification: Verify the correctness of the final design in meeting the specifications.

BCD-to-Seven-Segment Decoder

• LED 7-Segment Display:

  • Utilises Light-Emitting Diodes (LEDs).

  • A single digit display takes 7-bit inputs (plus one optional for the decimal point).

• BCD Representation:

  • Each decimal digit is represented using a 4-bit binary integer (BCD).

  • The BCD-to-Seven-Segment Decoder generates control signals for a display unit (Segments A, B, C, D, E, F, G).

• Control Signals:

  • Relationship between BCD digit and segmented outputs defined through a truth table.

Formulation in Detail

• Inputs/Outputs:

  • Inputs: decimal digit in BCD format (let A, B, C, D represent the bits).

  • Outputs: segments a, b, c, d, e, f, g for the display.

• Truth Table Example:

  • For BCD digit inputs, output segments are activated accordingly (e.g., 0 activates all segments except segment g).

Optimisation Techniques

• Goal: Reduce the number of gates:

  • Independent Implementation requires 27 AND gates and 7 OR gates.

  • Shared Implementation optimises to 14 AND and 7 OR gates by sharing common product terms, leading to simplified Boolean expressions.

Technology Mapping

• Mapping Components:

  • Use NAND gates and inverters for circuit implementation.

  • Techniques like DeMorgan’s theorem can simplify the circuit structure.

• Common Mappings:

  • NAND == AND + Inverter

  • NOR == OR + Inverter

4-Bit Equity Comparator

• Specification:

  • Compares two 4-bit numbers A and B.

  • Output E indicates equality (1 for equal, 0 for non-equal).

• Hierarchical Design:

  • Implement the comparator using smaller functional blocks for easier management and reuse.

• Optimisation Methods:

  • Combine individual bit comparisons into a single output E.

  • Utilize a logical diagram to represent comparison logic.

Verification Strategies

• Manual Verification:

  • Validate circuit functionality by referencing truth tables.

• Automated Verification:

  • Employ simulation tools to automate the verification against desired outputs.