x86 Processor Architecture

General Concepts

• Basic Microcomputer Design:
  • Clock: synchronizes CPU operations.
  • Control Unit (CU): coordinates sequence of execution steps.
  • Arithmetic Logic Unit (ALU): performs arithmetic and bitwise processing.
• Clock:
  • Synchronizes CPU and BUS operations.
  • Machine cycle measures the time of a single operation.
  • Used to trigger events.
• Instruction Execution Cycle:
  • Fetch: Retrieve the instruction from memory.
  • Decode: Interpret the instruction.
  • Fetch operands: Get the data required for the instruction.
  • Execute: Perform the operation.
  • Store output: Save the result.
• Reading from Memory: Requires multiple machine cycles because memory responds slower than the CPU.
  • Place the address of the value on the address bus.
  • Assert the processor’s RD (read) pin.
  • Wait one clock cycle for memory to respond.
  • Copy the data from the data bus into the destination operand.
• Cache Memory: High-speed static RAM inside and outside the CPU.
  • Level-1 cache: inside the CPU.
  • Level-2 cache: outside the CPU.
  • Cache hit: data found in cache.
  • Cache miss: data not found in cache.
• How a Program Runs:
  • User sends program name to the Operating System.
  • OS searches for program in the current directory and system path.
  • Gets starting cluster from the directory entry.
  • Loads and starts the program.

IA-32 Processor Architecture

• Modes of Operation:
  • Protected mode: native mode (Windows, Linux).
  • Real-address mode: native MS-DOS.
  • System Management Mode: power management, system security, diagnostics.
  • Virtual-8086 mode: hybrid of Protected; each program has its own 8086 computer.
• Basic Execution Environment:
  • Addressable memory.
  • General-purpose registers.
  • Index and base registers.
  • Specialized register uses.
  • Status flags.
  • Floating-point, MMX, XMM registers.
• Addressable Memory:
  • Protected mode: 4 GB, 32-bit address.
  • Real-address and Virtual-8086 modes: 1 MB space, 20-bit address.
• General-Purpose Registers: Named storage locations inside the CPU, optimized for speed.
• Accessing Parts of Registers: Use 8-bit name, 16-bit name, or 32-bit name. Applies to EAX, EBX, ECX, and EDX.
• Index and Base Registers: Some registers have only a 16-bit name for their lower half.
• Some Specialized Register Uses:
  • General-Purpose Registers:
    • EAX – accumulator.
    • ECX – loop counter.
    • ESP – stack pointer.
    • ESI, EDI – index registers.
    • EBP – extended frame pointer (stack).
  • Segment Registers:
    • CS – code segment.
    • DS – data segment.
    • SS – stack segment.
    • ES, FS, GS - additional segments.
  • EIP – instruction pointer.
  • EFLAGS: status and control flags; each flag is a single binary bit.
• Status Flags:
  • Carry: unsigned arithmetic out of range.
  • Overflow: signed arithmetic out of range.
  • Sign: result is negative.
  • Zero: result is zero.
  • Auxiliary Carry: carry from bit 3 to bit 4.
  • Parity: sum of 1 bits is an even number.
• Floating-Point, MMX, XMM Registers:
  • Eight 80-bit floating-point data registers: ST(0), ST(1), . . . , ST(7); arranged in a stack; used for all floating-point arithmetic.
  • Eight 64-bit MMX registers.
  • Eight 128-bit XMM registers for single-instruction multiple-data (SIMD) operations.

IA-32 Memory Management

• Real-address mode
• Calculating linear addresses
• Protected mode
• Multi-segment model
• Paging
• Protected Mode: (1 of 2)
  • 4 GB addressable RAM (00000000 to FFFFFFFFh).
  • Each program assigned a memory partition which is protected from other programs.
  • Designed for multitasking.
  • Supported by Linux & MS-Windows.

64-Bit Processors

• 64-Bit Operation Modes:
  • Compatibility mode: can run existing 16-bit and 32-bit applications (Windows supports only 32-bit apps in this mode).
  • 64-bit mode: Windows 64 uses this.
• Basic Execution Environment:
  • Addresses can be 64 bits (48 bits, in practice).
  • 16 64-bit general purpose registers.
  • 64-bit instruction pointer named RIP.
• 64-Bit General Purpose Registers:
  • 32-bit general purpose registers: EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP, R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D.
  • 64-bit general purpose registers: RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, R8, R9, R10, R11, R12, R13, R14, R15.

Components of an IA-32 Microcomputer

• Motherboard
• Video output
• Memory
• Input-output ports
• Motherboard:
  • CPU socket
  • External cache memory slots
  • Main memory slots
  • BIOS chips
  • Sound synthesizer chip (optional)
  • Video controller chip (optional)
  • IDE, parallel, serial, USB, video, keyboard, joystick, network, and mouse connectors
  • PCI bus connectors (expansion cards)
• Video Output:
  • Video controller: on motherboard, or on expansion card.
  • AGP (accelerated graphics port technology).
  • Video memory (VRAM).
  • Video CRT Display: uses raster scanning, horizontal retrace, vertical retrace.
  • Direct digital LCD monitors: no raster scanning required.
• Memory:
  • ROM: read-only memory.
  • EPROM: erasable programmable read-only memory.
  • Dynamic RAM (DRAM): inexpensive; must be refreshed constantly.
  • Static RAM (SRAM): expensive; used for cache memory; no refresh required.
  • Video RAM (VRAM): dual ported; optimized for constant video refresh.
  • CMOS RAM: complimentary metal-oxide semiconductor; system setup information.

Input-Output System

• USB (universal serial bus): intelligent high-speed connection to devices; up to 12 megabits/second; USB hub connects multiple devices; enumeration: computer queries devices; supports hot connections.
• Parallel: short cable, high speed; common for printers; bidirectional, parallel data transfer; Intel 8255 controller chip.
• Serial: RS-232 serial port; one bit at a time; uses long cables and modems; 16550 UART (universal asynchronous receiver transmitter); programmable in assembly language.
• Device Interfaces:
  • ATA host adapters: intelligent drive electronics (hard drive, CDROM).
  • SATA (Serial ATA): inexpensive, fast, bidirectional.
  • FireWire: high speed (800 MB/sec), many devices at once.
  • Bluetooth: small amounts of data, short distances, low power usage.
  • Wi-Fi (wireless Ethernet): IEEE 802.11 standard, faster than Bluetooth.
• Levels of Input-Output:
  • Level 3: High-level language function; examples: C++, Java; portable, convenient, not always the fastest.
  • Level 2: Operating system; Application Programming Interface (API); extended capabilities, lots of details to master.
  • Level 1: BIOS; drivers that communicate directly with devices; OS security may prevent application-level code from working at this level.
• Displaying a String of Characters When a HLL program displays a string of characters, the following steps take place:
• Programming levels Assembly language programs can perform input-output at each of the following levels:

Summary

• Central Processing Unit (CPU)
• Arithmetic Logic Unit (ALU)
• Instruction execution cycle
• Multitasking
• Floating Point Unit (FPU)
• Complex Instruction Set
• Real mode and Protected mode
• Motherboard components
• Memory types
• Input/Output and access levels